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-rw-r--r--testsuite/synth/issue2279/aggr1.vhdl17
1 files changed, 17 insertions, 0 deletions
diff --git a/testsuite/synth/issue2279/aggr1.vhdl b/testsuite/synth/issue2279/aggr1.vhdl
new file mode 100644
index 000000000..13a224d55
--- /dev/null
+++ b/testsuite/synth/issue2279/aggr1.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity aggr1 is
+ generic(
+ DATA_WIDTH : integer := 8
+ );
+ port (a : out std_logic_vector(DATA_WIDTH-1 downto 0);
+ b : out std_logic;
+ c : std_logic_vector(DATA_WIDTH+1-1 downto 0));
+end;
+
+architecture arch of aggr1 is
+begin
+ (a, b) <= c;
+end;
+