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Diffstat (limited to 'testsuite/synth/issue2089/bug.vhdl')
-rw-r--r-- | testsuite/synth/issue2089/bug.vhdl | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/testsuite/synth/issue2089/bug.vhdl b/testsuite/synth/issue2089/bug.vhdl new file mode 100644 index 000000000..b36b08786 --- /dev/null +++ b/testsuite/synth/issue2089/bug.vhdl @@ -0,0 +1,42 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug is +port( + clk : in std_ulogic +); +end entity; + +library IEEE; +use IEEE.std_logic_1164.all; + +entity ent is +port( + data : in std_ulogic_vector +); +end entity; + +architecture rtl of bug is + + type data_t is record + a : std_ulogic; + b : std_ulogic; + end record; + + function to_sulv(data : data_t) return std_ulogic_vector is + constant ret : std_ulogic_vector(1 downto 0) := data.a & data.b; + begin + return ret; + end function; + + constant data : data_t := (a => '0', b => '1'); +begin + u0 : entity work.ent + port map(data => to_sulv(data)); +end architecture; + +architecture rtl of ent is + +begin + +end architecture; |