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-rw-r--r--testsuite/synth/issue1454/tb_dummy_top.vhdl24
1 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/synth/issue1454/tb_dummy_top.vhdl b/testsuite/synth/issue1454/tb_dummy_top.vhdl
new file mode 100644
index 000000000..8aff91f8f
--- /dev/null
+++ b/testsuite/synth/issue1454/tb_dummy_top.vhdl
@@ -0,0 +1,24 @@
+entity tb_dummy_top is
+end tb_dummy_top;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dummy_top is
+ signal clk : std_logic;
+ signal d : std_logic;
+begin
+ dut: entity work.dummy_top
+ port map (clk, d);
+
+ process
+ begin
+ for i in 1 to 4 loop
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end loop;
+ wait;
+ end process;
+end behav;