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-rw-r--r--testsuite/synth/issue1421/repro4.vhdl16
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/synth/issue1421/repro4.vhdl b/testsuite/synth/issue1421/repro4.vhdl
new file mode 100644
index 000000000..4fa0f4738
--- /dev/null
+++ b/testsuite/synth/issue1421/repro4.vhdl
@@ -0,0 +1,16 @@
+entity repro3 is
+ port (clk : bit;
+ v : bit_vector (1 downto 0);
+ res : out bit_vector(1 downto 0));
+end;
+
+architecture behav of repro3 is
+begin
+ process (clk)
+ begin
+ if clk'event and clk = '1' then
+ res <= v;
+ end if;
+ res (0) <= '0';
+ end process;
+end behav;