diff options
Diffstat (limited to 'testsuite/synth/func02')
-rw-r--r-- | testsuite/synth/func02/func01.vhdl | 22 | ||||
-rw-r--r-- | testsuite/synth/func02/tb_func01.vhdl | 29 | ||||
-rwxr-xr-x | testsuite/synth/func02/testsuite.sh | 16 |
3 files changed, 67 insertions, 0 deletions
diff --git a/testsuite/synth/func02/func01.vhdl b/testsuite/synth/func02/func01.vhdl new file mode 100644 index 000000000..3d0155567 --- /dev/null +++ b/testsuite/synth/func02/func01.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity func01 is + port (a : std_logic_vector (7 downto 0); + b : out std_logic_vector (7 downto 0)); +end func01; + +architecture behav of func01 is + function gen_and (v : std_logic_vector (7 downto 0); + len : natural := 6) return std_logic_vector is + variable res : std_logic_vector (7 downto 0); + begin + res := (others => '0'); + res (len - 1 downto 0) := (others => '1'); + return res and v; + end gen_and; + +begin + b <= gen_and (a); +end behav; + diff --git a/testsuite/synth/func02/tb_func01.vhdl b/testsuite/synth/func02/tb_func01.vhdl new file mode 100644 index 000000000..3e9354625 --- /dev/null +++ b/testsuite/synth/func02/tb_func01.vhdl @@ -0,0 +1,29 @@ +entity tb_func01 is +end tb_func01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_func01 is + signal a, b : std_logic_vector(7 downto 0); +begin + dut: entity work.func01 + port map (a, b); + + process + begin + a <= x"5d"; + wait for 1 ns; + assert b = x"1d" severity failure; + + a <= x"ff"; + wait for 1 ns; + assert b = x"3f" severity failure; + + a <= x"c0"; + wait for 1 ns; + assert b = x"00" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/func02/testsuite.sh b/testsuite/synth/func02/testsuite.sh new file mode 100755 index 000000000..b30460585 --- /dev/null +++ b/testsuite/synth/func02/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in func01; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t --ieee-asserts=disable-at-0 + clean +done + +echo "Test successful" |