diff options
Diffstat (limited to 'testsuite/synth/case01')
-rw-r--r-- | testsuite/synth/case01/case01.vhdl | 28 | ||||
-rw-r--r-- | testsuite/synth/case01/case02.vhdl | 18 | ||||
-rw-r--r-- | testsuite/synth/case01/tb_case01.vhdl | 26 | ||||
-rw-r--r-- | testsuite/synth/case01/tb_case02.vhdl | 26 | ||||
-rwxr-xr-x | testsuite/synth/case01/testsuite.sh | 16 |
5 files changed, 114 insertions, 0 deletions
diff --git a/testsuite/synth/case01/case01.vhdl b/testsuite/synth/case01/case01.vhdl new file mode 100644 index 000000000..f20e41cb5 --- /dev/null +++ b/testsuite/synth/case01/case01.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity case01 is + port (a : std_logic_vector (4 downto 0); + o : out std_logic); +end case01; + +architecture behav of case01 is +begin + process (a) + begin + o <= '0'; + case a is + when "00011" => + o <= '1'; + when "00110" | "00111" | "10001" => + o <= '1'; + when "00100" => + when "01100" => + o <= '1'; + when "10000" => + o <= '1'; + when others => + o <= '0'; + end case; + end process; +end behav; diff --git a/testsuite/synth/case01/case02.vhdl b/testsuite/synth/case01/case02.vhdl new file mode 100644 index 000000000..3c1b08cbd --- /dev/null +++ b/testsuite/synth/case01/case02.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity case02 is + port (a : std_logic_vector (4 downto 0); + o : out std_logic); +end case02; + +architecture behav of case02 is +begin + with a select o <= + '1' when "00011", + '1' when "00110" | "00111" | "10001", + '0' when "00100", + '1' when "01100", + '1' when "10000", + '0' when others; +end behav; diff --git a/testsuite/synth/case01/tb_case01.vhdl b/testsuite/synth/case01/tb_case01.vhdl new file mode 100644 index 000000000..eb6bfa32b --- /dev/null +++ b/testsuite/synth/case01/tb_case01.vhdl @@ -0,0 +1,26 @@ +entity tb_case01 is +end tb_case01; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_case01 is + signal s : std_logic_vector (4 downto 0); + signal o : std_logic; +begin + dut: entity work.case01 + port map (s, o); + + process + constant ov : std_logic_vector (0 to 31) := + b"00010011000010001100000000000000"; + begin + for i in ov'range loop + s <= std_logic_vector(to_unsigned(i, 5)); + wait for 1 ns; + assert o = ov(i) severity failure; + end loop; + wait; + end process; +end behav; diff --git a/testsuite/synth/case01/tb_case02.vhdl b/testsuite/synth/case01/tb_case02.vhdl new file mode 100644 index 000000000..06b4b0789 --- /dev/null +++ b/testsuite/synth/case01/tb_case02.vhdl @@ -0,0 +1,26 @@ +entity tb_case02 is +end tb_case02; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_case02 is + signal s : std_logic_vector (4 downto 0); + signal o : std_logic; +begin + dut: entity work.case02 + port map (s, o); + + process + constant ov : std_logic_vector (0 to 31) := + b"00010011000010001100000000000000"; + begin + for i in ov'range loop + s <= std_logic_vector(to_unsigned(i, 5)); + wait for 1 ns; + assert o = ov(i) severity failure; + end loop; + wait; + end process; +end behav; diff --git a/testsuite/synth/case01/testsuite.sh b/testsuite/synth/case01/testsuite.sh new file mode 100755 index 000000000..ecb19a503 --- /dev/null +++ b/testsuite/synth/case01/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in case01 case02; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean +done + +echo "Test successful" |