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Diffstat (limited to 'testsuite/synth/arr02/arr03.vhdl')
-rw-r--r-- | testsuite/synth/arr02/arr03.vhdl | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/testsuite/synth/arr02/arr03.vhdl b/testsuite/synth/arr02/arr03.vhdl new file mode 100644 index 000000000..0363a2bda --- /dev/null +++ b/testsuite/synth/arr02/arr03.vhdl @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity arr03 is + port ( + a : std_logic_vector (31 downto 0); + sel : natural range 0 to 3; + clk : std_logic; + res : out std_logic_vector (3 downto 0)); +end arr03; + +architecture behav of arr03 is + type t_mem is array (0 to 3) of std_logic_vector (7 downto 0); + type t_stage is record + sel : natural range 0 to 3; + val : t_mem; + end record; + + signal s : t_stage; +begin + process (clk) is + begin + if rising_edge (clk) then + s.sel <= sel; + s.val <= (a (31 downto 24), + a (23 downto 16), + a (15 downto 8), + a (7 downto 0)); + end if; + end process; + + process (clk) is + begin + if rising_edge (clk) then + res <= s.val (s.sel)(6 downto 3); + end if; + end process; +end behav; |