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-rw-r--r--testsuite/pyunit/Current.vhdl2
1 files changed, 2 insertions, 0 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl
index f755b95a8..cd6537519 100644
--- a/testsuite/pyunit/Current.vhdl
+++ b/testsuite/pyunit/Current.vhdl
@@ -90,6 +90,8 @@ begin
if rising_edge(Clock) then
if Reset = '1' then
Q <= (others => '0');
+ elsif Load = '1' then
+ Q <= D after 10 ns;
else
Q <= std_logic_vector(unsigned(Q) + 1);
end if;