3 files changed, 40 insertions, 6 deletions
diff --git a/testsuite/gna/issue2422/testsuite.sh b/testsuite/gna/issue2422/testsuite.sh
index 19b226075..ba8fab5f2 100755
--- a/testsuite/gna/issue2422/testsuite.sh
+++ b/testsuite/gna/issue2422/testsuite.sh
@@ -12,16 +12,15 @@ elab_simulate aggr_repro3
 analyze aggr_repro4.vhdl
 elab_simulate aggr_repro4
 
+analyze_failure top.vhdl
+
 export GHDL_STD_FLAGS=--std=93c
 analyze aggr_repro2.vhdl
 elab_simulate aggr_repro2
 
-clean
-
-#export GHDL_STD_FLAGS=--std=08
-#analyze repro.vhdl
-#elab_simulate repro
+analyze top.vhdl
+elab_simulate top
 
-#clean
+clean
 
 echo "Test successful"
diff --git a/testsuite/gna/issue2422/top.vhdl b/testsuite/gna/issue2422/top.vhdl
new file mode 100644
index 000000000..c445a7aea
--- /dev/null
+++ b/testsuite/gna/issue2422/top.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use     ieee.std_logic_1164.all;
+use     ieee.numeric_std.all;
+
+entity comp is
+	port (
+		output : out unsigned
+	);
+end entity;
+
+architecture a1 of comp is
+begin
+	output <= (7 downto 0 => '0');  -- not using others due to issue #2421
+end architecture;
+
+
+
+
+library ieee;
+use     ieee.std_logic_1164.all;
+use     ieee.numeric_std.all;
+
+entity top is
+end entity;
+
+architecture a2 of top is
+	signal sig : std_logic_vector(7 downto 0);
+begin
+	inst : entity work.comp
+		port map (
+			std_logic_vector(output) => sig
+		);
+end architecture;
diff --git a/testsuite/gna/issue40/testsuite.sh b/testsuite/gna/issue40/testsuite.sh
index 91c95c926..74611179e 100755
--- a/testsuite/gna/issue40/testsuite.sh
+++ b/testsuite/gna/issue40/testsuite.sh
@@ -1,6 +1,8 @@
 #! /bin/sh
 
 . ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=93
 analyze_failure test.vhdl
 analyze_failure test2.vhdl