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-rw-r--r--testsuite/gna/issue737/ent4.vhdl13
1 files changed, 13 insertions, 0 deletions
diff --git a/testsuite/gna/issue737/ent4.vhdl b/testsuite/gna/issue737/ent4.vhdl
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+++ b/testsuite/gna/issue737/ent4.vhdl
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+entity ent4 is
+end entity;
+
+architecture impl of ent4 is
+ type bitvv is array(natural range <>) of bit_vector;
+ signal foo: bitvv(2 downto 0)(0 downto 0);
+ signal bar: bitvv(1 downto 0)(0 downto 0);
+begin
+
+foo(2 downto 1) <= bar;
+foo(0) <= foo(2);
+
+end architecture;