1 files changed, 32 insertions, 0 deletions
diff --git a/testsuite/gna/issue72/issue.vhdl b/testsuite/gna/issue72/issue.vhdl
new file mode 100644
index 000000000..9eb2132df
--- /dev/null
+++ b/testsuite/gna/issue72/issue.vhdl
@@ -0,0 +1,32 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.issue_pkg.t_one_two;           -- does not work
+--use work.issue_pkg.all;                 -- works
+
+entity issue is
+
+  port (
+    clk    : in  std_logic;
+    input  : in  t_one_two;
+    output : out std_logic
+    );
+
+end entity issue;
+
+architecture rtl of issue is
+
+begin  -- architecture rtl
+
+  process (clk) is
+  begin  -- process
+    if clk'event and clk = '1' then  -- rising clock edge
+      if input = one then
+        output <= '1';
+      else
+        output <= '0';
+      end if;
+    end if;
+  end process;
+
+end architecture rtl;