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-rw-r--r--testsuite/gna/issue672/SQR.vhd101
-rw-r--r--testsuite/gna/issue672/SQRTb.vhd91
-rw-r--r--testsuite/gna/issue672/sqrtb.ref123
-rwxr-xr-xtestsuite/gna/issue672/testsuite.sh19
4 files changed, 334 insertions, 0 deletions
diff --git a/testsuite/gna/issue672/SQR.vhd b/testsuite/gna/issue672/SQR.vhd
new file mode 100644
index 000000000..da393aed2
--- /dev/null
+++ b/testsuite/gna/issue672/SQR.vhd
@@ -0,0 +1,101 @@
+-------------------------------------------------------------------------------
+-- walter d. gallegos
+-- www.waltergallegos.com
+-- Programable Logic & Software
+-- Consultoria y Diseno
+--
+-- Este archivo y documentacion son propiedad intelectual de Walter D. Gallegos
+--
+-------------------------------------------------------------------------------
+-- Autor : WDG
+-- Fecha : 2018-10-04
+-- Archivo : SQR.vhd
+-- Notas :
+--
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL, IEEE.NUMERIC_STD.ALL;
+
+
+ENTITY SQR IS
+ PORT(
+ CLOCK : IN std_logic;
+ DIN : IN std_logic_vector(31 downto 0);
+ VIN : IN std_logic;
+ DOUT : OUT std_logic_vector(31 downto 0);
+ VOUT : OUT std_logic
+ );
+END ENTITY SQR;
+
+ARCHITECTURE REV0 OF SQR IS
+
+ CONSTANT busZero : STD_LOGIC_VECTOR(DIN'RANGE) := (OTHERS => '0');
+
+ SIGNAL a : UNSIGNED(DIN'RANGE);
+ SIGNAL c, sub : UNSIGNED(DIN'LEFT*2+1 DOWNTO 0);
+ SIGNAL i : INTEGER RANGE a'RANGE;
+ SIGNAL run : STD_LOGIC;
+
+BEGIN
+
+ sub <= c - a * a;
+
+ Registers : PROCESS(CLOCK)
+ BEGIN
+ IF rising_edge(CLOCK) THEN
+ IF VIN = '1' THEN
+ i <= a'LEFT; run <= '1';
+ a <= (a'LEFT => '1', OTHERS => '0'); c <= UNSIGNED(DIN & busZero);
+ ELSIF run = '1' THEN
+ IF i > 0 THEN i <= i - 1;
+ a(i) <= NOT(sub(sub'LEFT)); a(i-1) <= '1';
+ ELSE
+ a(i) <= NOT(sub(sub'LEFT));
+ run <= '0';
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS Registers;
+
+ DOUT <= STD_LOGIC_VECTOR(a);
+ VOUT <= NOT(run);
+
+END REV0;
+
+--ARCHITECTURE REV1 OF SQR IS
+--
+-- CONSTANT busZero : STD_LOGIC_VECTOR(17 DOWNTO 0) := (OTHERS => '0');
+-- CONSTANT busZero2: STD_LOGIC_VECTOR(DIN'LEFT-18 DOWNTO 0) := (OTHERS => '0');
+--
+-- SIGNAL a : UNSIGNED(17 DOWNTO 0);
+-- SIGNAL c, sub : UNSIGNED(a'LEFT*2+1 DOWNTO 0);
+-- SIGNAL i : INTEGER RANGE a'RANGE;
+-- SIGNAL run : STD_LOGIC;
+--
+--BEGIN
+--
+-- sub <= c - a * a;
+--
+-- Registers : PROCESS(CLOCK)
+-- BEGIN
+-- IF rising_edge(CLOCK) THEN
+-- IF VIN = '1' THEN
+-- i <= a'LEFT; run <= '1';
+-- a <= (a'LEFT => '1', OTHERS => '0'); c <= UNSIGNED(DIN(17 DOWNTO 0) & busZero);
+-- ELSIF run = '1' THEN
+-- IF i > 0 THEN i <= i - 1;
+-- a(i) <= NOT(sub(sub'LEFT)); a(i-1) <= '1';
+-- ELSE
+-- a(i) <= NOT(sub(sub'LEFT));
+-- run <= '0';
+-- END IF;
+-- END IF;
+-- END IF;
+-- END PROCESS Registers;
+
+-- DOUT <= busZero2 & STD_LOGIC_VECTOR(a);
+-- VOUT <= NOT(run);
+--
+--END REV1; \ No newline at end of file
diff --git a/testsuite/gna/issue672/SQRTb.vhd b/testsuite/gna/issue672/SQRTb.vhd
new file mode 100644
index 000000000..e4b1989f3
--- /dev/null
+++ b/testsuite/gna/issue672/SQRTb.vhd
@@ -0,0 +1,91 @@
+-------------------------------------------------------------------------------
+-- walter d. gallegos
+-- www.waltergallegos.com
+-- Programable Logic & Software
+-- Consultoria y Diseno
+--
+-- Este archivo y documentacion son propiedad intelectual de Walter D. Gallegos
+--
+-------------------------------------------------------------------------------
+-- Autor : WDG
+-- Fecha : 2018-09-21
+-- Archivo : SPITb.vhd
+-- Notas :
+--
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL, IEEE.NUMERIC_STD.ALL;
+
+ENTITY SQRTb IS
+END SQRTb;
+
+ARCHITECTURE TB OF SQRTb IS
+
+ CONSTANT tCyc : TIME := 50 ns;
+
+ COMPONENT SQR
+ PORT (
+ CLOCK : IN std_logic;
+ DIN : IN std_logic_vector(31 downto 0);
+ VIN : IN std_logic;
+ DOUT : OUT std_logic_vector(31 downto 0);
+ VOUT : OUT std_logic
+ );
+ END COMPONENT SQR;
+
+ SIGNAL clock, vIn, vOut : STD_LOGIC;
+ SIGNAL dIn, dOut : STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+ PROCEDURE Transfer(
+ d : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ SIGNAL clock : IN STD_LOGIC;
+ SIGNAL di : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ SIGNAL vOut : IN STD_LOGIC;
+ SIGNAL vIn : OUT STD_LOGIC) IS
+ BEGIN
+ WAIT UNTIL rising_edge(CLOCK);
+ WAIT FOR 1 ns; di <= d;
+ WAIT FOR 1 ns; Vin <= '1';
+ WAIT FOR tCyc; vIn <= '0';
+ WAIT FOR 1 ns;
+ WAIT UNTIL vOut = '1';
+ END PROCEDURE Transfer;
+
+BEGIN
+
+ ClockGen : PROCESS
+ BEGIN
+ clock <= '0'; WAIT FOR tCyc/2;
+ clock <= '1'; WAIT FOR tCyc/2;
+ END PROCESS ClockGen;
+
+ A0 : SQR
+ PORT MAP (
+ CLOCK => clock,
+ DIN => dIn,
+ VIN => vIn,
+ DOUT => dOut,
+ VOUT => vOut
+ );
+
+ Stim : PROCESS
+ BEGIN
+ vIn <= '0';
+ WAIT FOR 100 ns; Transfer(x"00002000", clock, dIn, vOut, vIn );
+ WAIT FOR 200 ns; Transfer(x"00003000", clock, dIn, vOut, vIn );
+ WAIT FOR 100 ns; Transfer(x"00004000", clock, dIn, vOut, vIn );
+ WAIT FOR 100 ns; Transfer(x"08004000", clock, dIn, vOut, vIn );
+ WAIT;
+ END PROCESS Stim;
+
+END TB;
+
+CONFIGURATION Default OF SQRTb IS
+ FOR TB
+ FOR A0 : SQR
+ USE ENTITY work.SQR(REV0);
+ END FOR;
+ END FOR;
+END Default; \ No newline at end of file
diff --git a/testsuite/gna/issue672/sqrtb.ref b/testsuite/gna/issue672/sqrtb.ref
new file mode 100644
index 000000000..1d5838406
--- /dev/null
+++ b/testsuite/gna/issue672/sqrtb.ref
@@ -0,0 +1,123 @@
+Now is 0ms +0
+Now is 25ns +0
+Now is 25ns +1
+Now is 50ns +0
+Now is 50ns +1
+Now is 75ns +0
+Now is 75ns +1
+Now is 100ns +0
+Now is 100ns +1
+Now is 125ns +0
+Now is 125ns +1
+Now is 126ns +0
+Now is 126ns +1
+Now is 127ns +0
+Now is 127ns +1
+Now is 150ns +0
+Now is 150ns +1
+Now is 175ns +0
+Now is 175ns +1
+Now is 175ns +2
+Now is 175ns +3
+Now is 177ns +0
+Now is 177ns +1
+Now is 178ns +0
+Now is 200ns +0
+Now is 200ns +1
+Now is 225ns +0
+Now is 225ns +1
+Now is 225ns +2
+Now is 225ns +3
+Now is 250ns +0
+Now is 250ns +1
+Now is 275ns +0
+Now is 275ns +1
+Now is 275ns +2
+Now is 275ns +3
+Now is 300ns +0
+Now is 300ns +1
+Now is 325ns +0
+Now is 325ns +1
+Now is 325ns +2
+Now is 325ns +3
+Now is 350ns +0
+Now is 350ns +1
+Now is 375ns +0
+Now is 375ns +1
+Now is 375ns +2
+Now is 375ns +3
+Now is 400ns +0
+Now is 400ns +1
+Now is 425ns +0
+Now is 425ns +1
+Now is 425ns +2
+Now is 425ns +3
+Now is 450ns +0
+Now is 450ns +1
+Now is 475ns +0
+Now is 475ns +1
+Now is 475ns +2
+Now is 475ns +3
+Now is 500ns +0
+Now is 500ns +1
+Now is 525ns +0
+Now is 525ns +1
+Now is 525ns +2
+Now is 525ns +3
+Now is 550ns +0
+Now is 550ns +1
+Now is 575ns +0
+Now is 575ns +1
+Now is 575ns +2
+Now is 575ns +3
+Now is 600ns +0
+Now is 600ns +1
+Now is 625ns +0
+Now is 625ns +1
+Now is 625ns +2
+Now is 625ns +3
+Now is 650ns +0
+Now is 650ns +1
+Now is 675ns +0
+Now is 675ns +1
+Now is 675ns +2
+Now is 675ns +3
+Now is 700ns +0
+Now is 700ns +1
+Now is 725ns +0
+Now is 725ns +1
+Now is 725ns +2
+Now is 725ns +3
+Now is 750ns +0
+Now is 750ns +1
+Now is 775ns +0
+Now is 775ns +1
+Now is 775ns +2
+Now is 775ns +3
+Now is 800ns +0
+Now is 800ns +1
+Now is 825ns +0
+Now is 825ns +1
+Now is 825ns +2
+Now is 825ns +3
+Now is 850ns +0
+Now is 850ns +1
+Now is 875ns +0
+Now is 875ns +1
+Now is 875ns +2
+Now is 875ns +3
+Now is 900ns +0
+Now is 900ns +1
+Now is 925ns +0
+Now is 925ns +1
+Now is 925ns +2
+Now is 925ns +3
+Now is 950ns +0
+Now is 950ns +1
+Now is 975ns +0
+Now is 975ns +1
+Now is 975ns +2
+Now is 975ns +3
+Now is 1us +0
+Now is 1us +1
+info: simulation stopped by --stop-time @1us
diff --git a/testsuite/gna/issue672/testsuite.sh b/testsuite/gna/issue672/testsuite.sh
new file mode 100755
index 000000000..fb7eaa96b
--- /dev/null
+++ b/testsuite/gna/issue672/testsuite.sh
@@ -0,0 +1,19 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze SQR.vhd SQRTb.vhd
+elab sqrtb
+simulate sqrtb --stop-time=1us
+
+if ! simulate --time-resolution=fs sqrtb --stop-time=1us; then
+ echo "skip --time-resolution tests"
+else
+ simulate --time-resolution=ns sqrtb --stop-time=1us --disp-time | sed -e 's/.*info/info/' > sqrtb.out
+ diff --strip-trailing-cr sqrtb.ref sqrtb.out
+fi
+
+rm -f sqrtb.out
+clean
+
+echo "Test successful"