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-rw-r--r--testsuite/gna/issue1697/e1.vhdl10
1 files changed, 10 insertions, 0 deletions
diff --git a/testsuite/gna/issue1697/e1.vhdl b/testsuite/gna/issue1697/e1.vhdl
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+++ b/testsuite/gna/issue1697/e1.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity e is
+ port (i : in std_logic_vector(2 downto 0) := ('1','0'));
+end entity;
+
+architecture a of e is
+begin
+end architecture;