1 files changed, 19 insertions, 0 deletions
diff --git a/testsuite/gna/issue151/tb.vhdl b/testsuite/gna/issue151/tb.vhdl
new file mode 100644
index 000000000..8aadd3f4b
--- /dev/null
+++ b/testsuite/gna/issue151/tb.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+ port (in_vec   : in std_logic_vector);
+end entity;
+
+architecture rtl of test is
+signal A : natural;
+begin
+
+  gen2 : if in_vec'length <= 2 generate
+     A <= 2;
+  end generate;
+  gen3 : if in_vec'length > 2 generate
+     A <= 3;
+  end generate;
+end architecture;