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-rw-r--r--testsuite/gna/issue1379/bar.vhdl36
1 files changed, 36 insertions, 0 deletions
diff --git a/testsuite/gna/issue1379/bar.vhdl b/testsuite/gna/issue1379/bar.vhdl
new file mode 100644
index 000000000..391870d3b
--- /dev/null
+++ b/testsuite/gna/issue1379/bar.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity foo is
+ generic (
+ LENGTH : natural
+ );
+ port (
+ input : in std_logic_vector(LENGTH - 1 downto 0)
+ );
+end foo;
+
+architecture behave of foo is
+begin
+end behave;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity bar is
+end entity bar;
+
+architecture behave of bar is
+ component foo is
+ port (
+ input : in std_logic_vector(7 downto 0)
+ );
+ end component;
+
+begin
+
+ my_foo : foo
+ port map (
+ input => (others => '0')
+ );
+end behave;