diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-expands.adb | 29 | ||||
| -rw-r--r-- | src/synth/netlists-inference.adb | 5 | ||||
| -rw-r--r-- | src/synth/netlists-memories.adb | 5 | ||||
| -rw-r--r-- | src/synth/synth-environment.adb | 6 | ||||
| -rw-r--r-- | src/synth/synth-expr.adb | 24 | ||||
| -rw-r--r-- | src/synth/synth-insts.adb | 12 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 12 | ||||
| -rw-r--r-- | src/synth/synth-stmts.adb | 97 |
8 files changed, 134 insertions, 56 deletions
diff --git a/src/synth/netlists-expands.adb b/src/synth/netlists-expands.adb index 571b17620..fe7687014 100644 --- a/src/synth/netlists-expands.adb +++ b/src/synth/netlists-expands.adb @@ -170,13 +170,16 @@ package body Netlists.Expands is procedure Truncate_Address (Ctxt : Context_Acc; Addr : in out Net; Nbr_Els : Natural) is + Loc : Location_Type; Addr_Len : Width; begin Addr_Len := Uns32 (Clog2 (Uns64 (Nbr_Els))); if Get_Width (Addr) > Addr_Len then -- Truncate the address. This is requied so that synth_case doesn't -- use default value. + Loc := Get_Location (Get_Net_Parent (Addr)); Addr := Build_Trunc (Ctxt, Id_Utrunc, Addr, Addr_Len); + Set_Location (Addr, Loc); end if; end Truncate_Address; @@ -229,8 +232,10 @@ package body Netlists.Expands is Free_Case_Element_Array (Els); end Expand_Dyn_Extract; - procedure Generate_Decoder - (Ctxt : Context_Acc; Addr : Net; Net_Arr : out Net_Array) + procedure Generate_Decoder (Ctxt : Context_Acc; + Addr : Net; + Net_Arr : out Net_Array; + Loc : Location_Type) is W : constant Width := Get_Width (Addr); V0, V1 : Net; @@ -245,7 +250,9 @@ package body Netlists.Expands is for I in reverse 0 .. W - 1 loop V1 := Build_Extract_Bit (Ctxt, Addr, I); + Set_Location (V1, Loc); V0 := Build_Monadic (Ctxt, Id_Not, V1); + Set_Location (V0, Loc); Step := 2**Natural (I); if I = W - 1 then Net_Arr (0) := V0; @@ -255,9 +262,11 @@ package body Netlists.Expands is loop V := Net_Arr (J); Net_Arr (J) := Build_Dyadic (Ctxt, Id_And, V, V0); + Set_Location (Net_Arr (J), Loc); J := J + Step; exit when J > Net_Arr'Last; Net_Arr (J) := Build_Dyadic (Ctxt, Id_And, V, V1); + Set_Location (Net_Arr (J), Loc); J := J + Step; exit when J > Net_Arr'Last; end loop; @@ -272,6 +281,7 @@ package body Netlists.Expands is Dat : Net; Memidx_Arr : Memidx_Array_Type; Net_Arr : Net_Array; + Loc : Location_Type; En : Net := No_Net) is Dat_W : constant Width := Get_Width (Dat); @@ -352,9 +362,11 @@ package body Netlists.Expands is S := Net_Arr (Sel); if En /= No_Net then S := Build_Dyadic (Ctxt, Id_And, S, En); + Set_Location (S, Loc); end if; V := Build_Mux2 (Ctxt, S, V, Dat); + Set_Location (V, Loc); Prev_Net := V; Next_Off := Off + Dat_W; @@ -384,10 +396,10 @@ package body Netlists.Expands is procedure Expand_Dyn_Insert (Ctxt : Context_Acc; Inst : Instance; En : Net) is + Loc : constant Location_Type := Get_Location (Inst); Mem : constant Net := Get_Input_Net (Inst, 0); Dat : constant Net := Get_Input_Net (Inst, 1); Addr_Net : constant Net := Get_Input_Net (Inst, 2); - -- Loc : constant Location_Type := Get_Location (Inst); O : constant Net := Get_Output (Inst, 0); O_W : constant Width := Get_Width (O); -- 1. compute number of dims, check order. @@ -410,7 +422,7 @@ package body Netlists.Expands is Disconnect (Get_Input (Inst, 2)); Extract_Address (Ctxt, Addr_Net, Ndims, Addr); Truncate_Address (Ctxt, Addr, Nbr_Els); - Generate_Decoder (Ctxt, Addr, Net_Arr.all); + Generate_Decoder (Ctxt, Addr, Net_Arr.all, Loc); -- Build muxes declare @@ -418,7 +430,7 @@ package body Netlists.Expands is begin Off := Get_Param_Uns32 (Inst, 0); Generate_Muxes - (Ctxt, Concat, Mem, Off, Dat, Memidx_Arr, Net_Arr.all, En); + (Ctxt, Concat, Mem, Off, Dat, Memidx_Arr, Net_Arr.all, Loc, En); if Off < O_W then Append (Concat, Build_Extract (Ctxt, Mem, Off, O_W - Off)); end if; @@ -438,12 +450,13 @@ package body Netlists.Expands is Remove_Instance (Inst); end Expand_Dyn_Insert; - -- Replase instance INST a ROT b by: S (a, b) | C (a, l - b) + -- Replace instance INST a ROT b by: S (a, b) | C (a, l - b) -- (S for shifted, C for counter-shifted) procedure Expand_Rot (Ctxt : Context_Acc; Inst : Instance; Id_S, Id_C : Shift_Module_Id) is + Loc : constant Location_Type := Get_Location (Inst); Val : constant Input := Get_Input (Inst, 0); Amt : constant Input := Get_Input (Inst, 1); Val_N : constant Net := Get_Driver (Val); @@ -456,11 +469,15 @@ package body Netlists.Expands is Res : Net; begin Sh_S := Build_Shift_Rotate (Ctxt, Id_S, Val_N, Amt_N); + Set_Location (Sh_S, Loc); R_Amt := Build_Dyadic (Ctxt, Id_Sub, Build_Const_UB32 (Ctxt, W_Val, W_Amt), Build2_Uresize (Ctxt, Amt_N, W_Amt)); + Set_Location (R_Amt, Loc); Sh_C := Build_Shift_Rotate (Ctxt, Id_C, Val_N, R_Amt); + Set_Location (Sh_C, Loc); Res := Build_Dyadic (Ctxt, Id_Or, Sh_S, Sh_C); + Set_Location (Res, Loc); Redirect_Inputs (Get_Output (Inst, 0), Res); Disconnect (Val); diff --git a/src/synth/netlists-inference.adb b/src/synth/netlists-inference.adb index 9ec445901..9079a260d 100644 --- a/src/synth/netlists-inference.adb +++ b/src/synth/netlists-inference.adb @@ -198,6 +198,7 @@ package body Netlists.Inference is Connect (I2, N1); else N4 := Build_Dyadic (Ctxt, Id_And, N2, N1); + Copy_Location (N4, Inst); Connect (I1, N4); end if; end; @@ -586,13 +587,16 @@ package body Netlists.Inference is -- Add the negation of the condition to the enable signal. -- Negate the condition for the current reset. Mux_Not_Rst := Build_Monadic (Ctxt, Id_Not, Mux_Rst); + Set_Location (Mux_Not_Rst, Stmt); if Rst /= No_Net then Rst := Build_Dyadic (Ctxt, Id_And, Rst, Mux_Not_Rst); + Set_Location (Rst, Stmt); end if; if Enable = No_Net then Enable := Mux_Not_Rst; else Enable := Build_Dyadic (Ctxt, Id_And, Enable, Mux_Not_Rst); + Set_Location (Enable, Stmt); end if; if Prev_Mux /= No_Instance then @@ -618,6 +622,7 @@ package body Netlists.Inference is else -- New async reset condition. Rst := Build_Dyadic (Ctxt, Id_Or, Mux_Rst, Rst); + Copy_Location (Rst, Mux_Rst); -- Use prev_mux to select the reset value. Connect (Get_Mux2_Sel (Prev_Mux), Mux_Rst); diff --git a/src/synth/netlists-memories.adb b/src/synth/netlists-memories.adb index b6523bdd9..31767e09d 100644 --- a/src/synth/netlists-memories.adb +++ b/src/synth/netlists-memories.adb @@ -498,6 +498,7 @@ package body Netlists.Memories is En := Get_Driver (Mux_En_Inp); if Dff_Out = Get_Driver (Mux_I1_Inp) then En := Build_Monadic (Ctxt, Id_Not, En); + Copy_Location (En, Iinst); end if; Disconnect (Mux_En_Inp); Disconnect (Mux_I0_Inp); @@ -575,6 +576,7 @@ package body Netlists.Memories is En := Get_Driver (Mux_En_Inp); if Dff_Out = Get_Driver (Mux_I1_Inp) then En := Build_Monadic (Ctxt, Id_Not, En); + Copy_Location (En, Dff_Inst); end if; Disconnect (Mux_En_Inp); Disconnect (Mux_I0_Inp); @@ -583,6 +585,7 @@ package body Netlists.Memories is Disconnect (Clk_Inp); Remove_Instance (Iinst); Res := Build_Mem_Rd_Sync (Ctxt, Last, Addr, Clk, En, Step); + Set_Location (Res, Get_Location (Dff_Inst)); -- Slice the output. N := Get_Output (Res, 1); @@ -2205,6 +2208,7 @@ package body Netlists.Memories is Drv := Drv0; Src := Drv1; Sel := Build_Monadic (Ctxt, Id_Not, Sel); + Copy_Location (Sel, Mux); elsif Has_One_Connection (Drv1) and then not Has_One_Connection (Drv0) then Disconnect (In0); @@ -2219,6 +2223,7 @@ package body Netlists.Memories is if Psel /= No_Net then Sel := Build_Dyadic (Ctxt, Id_And, Psel, Sel); + Copy_Location (Sel, Psel); end if; -- Reduce Drv until Src. diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb index 03acc2478..cf5384eb3 100644 --- a/src/synth/synth-environment.adb +++ b/src/synth/synth-environment.adb @@ -1278,11 +1278,13 @@ package body Synth.Environment is Res := N1_Net; Disconnect (N1_Sel); N1_Sel_Net := Build_Dyadic (Ctxt, Id_And, Sel, N1_Sel_Net); + Set_Location (N1_Sel_Net, Stmt); Connect (N1_Sel, N1_Sel_Net); else + Res := Build_Dyadic (Ctxt, Id_And, Sel, N1_Sel_Net); + Set_Location (Res, Stmt); Res := Build_Mux2 - (Ctxt, Build_Dyadic (Ctxt, Id_And, Sel, N1_Sel_Net), - N (0), Get_Driver (Get_Mux2_I1 (N1_Inst))); + (Ctxt, Res, N (0), Get_Driver (Get_Mux2_I1 (N1_Inst))); end if; end; elsif N (0) = N (1) then diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 49901c3db..00c69cb13 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -1514,29 +1514,38 @@ package body Synth.Expr is function Extract_Clock_Level (Syn_Inst : Synth_Instance_Acc; Expr : Node; Prefix : Node) return Net is + Ctxt : constant Context_Acc := Get_Build (Syn_Inst); Clk : Net; Imp : Node; Left, Right : Node; Lit : Node; Posedge : Boolean; + Res : Net; begin Clk := Get_Net (Synth_Name (Syn_Inst, Prefix)); if Get_Kind (Expr) /= Iir_Kind_Equality_Operator then Error_Msg_Synth (+Expr, "ill-formed clock-level, '=' expected"); - return Build_Posedge (Build_Context, Clk); + Res := Build_Posedge (Ctxt, Clk); + Set_Location (Res, Expr); + return Res; end if; Imp := Get_Implementation (Expr); if Get_Implicit_Definition (Imp) /= Iir_Predefined_Enum_Equality then Error_Msg_Synth (+Expr, "ill-formed clock-level, '=' expected"); - return Build_Posedge (Build_Context, Clk); + Res := Build_Posedge (Ctxt, Clk); + Set_Location (Res, Expr); + return Res; end if; Left := Get_Left (Expr); Right := Get_Right (Expr); if Get_Kind (Right) /= Iir_Kind_Character_Literal then Error_Msg_Synth (+Expr, "ill-formed clock-level, '0' or '1' expected"); - return Build_Posedge (Build_Context, Clk); + Res := Build_Posedge (Ctxt, Clk); + Set_Location (Res, Expr); + return Res; end if; + Lit := Get_Named_Entity (Right); if Lit = Vhdl.Std_Package.Bit_0 or else Lit = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_0 @@ -1552,14 +1561,15 @@ package body Synth.Expr is Posedge := True; end if; if not Is_Same_Node (Prefix, Left) then - Error_Msg_Synth - (+Left, "clock signal name doesn't match"); + Error_Msg_Synth (+Left, "clock signal name doesn't match"); end if; if Posedge then - return Build_Posedge (Build_Context, Clk); + Res := Build_Posedge (Ctxt, Clk); else - return Build_Negedge (Build_Context, Clk); + Res := Build_Negedge (Ctxt, Clk); end if; + Set_Location (Res, Expr); + return Res; end Extract_Clock_Level; -- Try to match: clk'event and clk = X diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index b7a520287..090760168 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -1019,8 +1019,11 @@ package body Synth.Insts is (Syn_Inst, Stmt, Comp, Null_Node, Null_Node); end Synth_Blackbox_Instantiation_Statement; - procedure Create_Component_Wire - (Ctxt : Context_Acc; Inter : Node; Val : Valtyp; Pfx_Name : Sname) + procedure Create_Component_Wire (Ctxt : Context_Acc; + Inter : Node; + Val : Valtyp; + Pfx_Name : Sname; + Loc : Source.Syn_Src) is Value : Net; W : Width; @@ -1032,6 +1035,7 @@ package body Synth.Insts is W := Get_Type_Width (Val.Typ); Value := Build_Signal (Ctxt, New_Internal_Name (Ctxt, Pfx_Name), W); + Set_Location (Value, Loc); Set_Wire_Gate (Val.Val.W, Value); when others => raise Internal_Error; @@ -1100,7 +1104,8 @@ package body Synth.Insts is | Port_Inout => Val := Create_Value_Wire (No_Wire_Id, Inter_Typ); Create_Component_Wire - (Get_Build (Syn_Inst), Assoc_Inter, Val, Inst_Name); + (Get_Build (Syn_Inst), Assoc_Inter, Val, Inst_Name, + Assoc); end case; Create_Object (Comp_Inst, Assoc_Inter, Val); end if; @@ -1153,6 +1158,7 @@ package body Synth.Insts is Inst := New_Instance (Get_Instance_Module (Syn_Inst), Inst_Obj.M, Inst_Name); + Set_Location (Inst, Stmt); Synth_Instantiate_Module (Comp_Inst, Inst, Inst_Obj, Get_Port_Map_Aspect_Chain (Bind)); diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index fd4966794..148886688 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -610,6 +610,7 @@ package body Synth.Oper is Nr1 := Build_Monadic (Ctxt, Id_Neg, R1); Set_Location (Nr1, Expr); Nn := Build_Shift_Rotate (Ctxt, Sh_Neg, L1, Nr1); + Set_Location (Nn, Expr); -- Extract the sign bit. Cond := Build_Extract (Ctxt, R1, Get_Width (R1) - 1, 1); @@ -1544,6 +1545,7 @@ package body Synth.Oper is Edge : Net; begin Edge := Build_Posedge (Ctxt, Get_Net (L)); + Set_Location (Edge, Expr); return Create_Value_Net (Edge, Res_Typ); end; when Iir_Predefined_Ieee_1164_Falling_Edge => @@ -1551,6 +1553,7 @@ package body Synth.Oper is Edge : Net; begin Edge := Build_Negedge (Ctxt, Get_Net (L)); + Set_Location (Edge, Expr); return Create_Value_Net (Edge, Res_Typ); end; when Iir_Predefined_Ieee_1164_Scalar_Is_X @@ -1653,8 +1656,13 @@ package body Synth.Oper is when Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Slv | Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Suv => - return Create_Value_Net - (Build_Reduce (Ctxt, Id_Red_Or, Get_Net (L)), Res_Typ); + declare + N : Net; + begin + N := Build_Reduce (Ctxt, Id_Red_Or, Get_Net (L)); + Set_Location (N, Expr); + return Create_Value_Net (N, Res_Typ); + end; when Iir_Predefined_Ieee_Numeric_Std_Match_Suv | Iir_Predefined_Ieee_Numeric_Std_Match_Slv => diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 61833ab58..d94095a5b 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -1674,6 +1674,18 @@ package body Synth.Stmts is pragma Assert (Nbr_Inout = Infos'Last); end Synth_Subprogram_Back_Association; + function Build_Control_Signal (Syn_Inst : Synth_Instance_Acc; + W : Width; + Loc : Source.Syn_Src) return Net + is + Res : Net; + begin + Res := Build_Signal + (Get_Build (Syn_Inst), New_Internal_Name (Build_Context), W); + Set_Location (Res, Loc); + return Res; + end Build_Control_Signal; + function Synth_Dynamic_Subprogram_Call (Syn_Inst : Synth_Instance_Acc; Sub_Inst : Synth_Instance_Acc; Call : Node; @@ -1717,21 +1729,17 @@ package body Synth.Stmts is C.Ret_Typ := Get_Subtype_Object (Syn_Inst, Get_Return_Type (Imp)); Set_Wire_Gate (C.W_Val, - Build_Signal (Build_Context, - New_Internal_Name (Build_Context), - C.Ret_Typ.W)); + Build_Control_Signal (Sub_Inst, C.Ret_Typ.W, Imp)); C.Ret_Init := Build_Const_X (Build_Context, C.Ret_Typ.W); Phi_Assign_Net (Build_Context, C.W_Val, C.Ret_Init, 0); end if; Set_Wire_Gate - (C.W_En, Build_Signal (Build_Context, - New_Internal_Name (Build_Context), 1)); + (C.W_En, Build_Control_Signal (Sub_Inst, 1, Imp)); Phi_Assign_Net (Build_Context, C.W_En, Get_Inst_Bit1 (Syn_Inst), 0); Set_Wire_Gate - (C.W_Ret, Build_Signal (Build_Context, - New_Internal_Name (Build_Context), 1)); + (C.W_Ret, Build_Control_Signal (Sub_Inst, 1, Imp)); Phi_Assign_Net (Build_Context, C.W_Ret, Get_Inst_Bit1 (Syn_Inst), 0); Decls.Synth_Declarations (C.Inst, Get_Declaration_Chain (Bod), True); @@ -2000,9 +2008,7 @@ package body Synth.Stmts is if (Lc.Prev_Loop /= null and then Lc.Prev_Loop.Need_Quit) then Lc.W_Quit := Alloc_Wire (Wire_Variable, Lc.Loop_Stmt); - Set_Wire_Gate - (Lc.W_Quit, Build_Signal (Get_Build (C.Inst), - New_Internal_Name (Build_Context), 1)); + Set_Wire_Gate (Lc.W_Quit, Build_Control_Signal (C.Inst, 1, Stmt)); Phi_Assign_Net (Get_Build (C.Inst), Lc.W_Quit, Get_Inst_Bit1 (C.Inst), 0); end if; @@ -2015,9 +2021,7 @@ package body Synth.Stmts is if Get_Exit_Flag (Stmt) then -- Exit statement for this loop. Lc.W_Exit := Alloc_Wire (Wire_Variable, Lc.Loop_Stmt); - Set_Wire_Gate - (Lc.W_Exit, Build_Signal (Get_Build (C.Inst), - New_Internal_Name (Build_Context), 1)); + Set_Wire_Gate (Lc.W_Exit, Build_Control_Signal (C.Inst, 1, Stmt)); Phi_Assign_Net (Get_Build (C.Inst), Lc.W_Exit, Get_Inst_Bit1 (C.Inst), 0); end if; @@ -2738,9 +2742,7 @@ package body Synth.Stmts is Synth_Declarations (C.Inst, Decls_Chain); end if; - Set_Wire_Gate (C.W_En, Build_Signal (Build_Context, - New_Internal_Name (Build_Context), - 1)); + Set_Wire_Gate (C.W_En, Build_Control_Signal (Syn_Inst, 1, Proc)); Phi_Assign_Net (Build_Context, C.W_En, Get_Inst_Bit1 (Syn_Inst), 0); case Iir_Kinds_Process_Statement (Get_Kind (Proc)) is @@ -2866,6 +2868,10 @@ package body Synth.Stmts is is use PSL.Types; use PSL.Nodes; + + Ctxt : constant Context_Acc := Get_Build (Syn_Inst); + Loc : constant Location_Type := Get_Location (Expr); + Res : Net; begin case Get_Kind (Expr) is when N_HDL_Bool => @@ -2875,10 +2881,12 @@ package body Synth.Stmts is return Get_Net (Synth_Expression (Syn_Inst, E)); end; when N_Not_Bool => - return Build_Monadic - (Build_Context, Netlists.Gates.Id_Not, + pragma Assert (Loc /= No_Location); + Res := Build_Monadic + (Ctxt, Netlists.Gates.Id_Not, Synth_PSL_Expression (Syn_Inst, Get_Boolean (Expr))); when N_And_Bool => + pragma Assert (Loc /= No_Location); declare L : constant PSL_Node := Get_Left (Expr); R : constant PSL_Node := Get_Right (Expr); @@ -2894,32 +2902,37 @@ package body Synth.Stmts is end if; if Get_Kind (R) = N_EOS then -- It is never EOS! - return Build_Const_UB32 (Build_Context, 0, 1); + Res := Build_Const_UB32 (Build_Context, 0, 1); + else + Res := Build_Dyadic (Ctxt, Netlists.Gates.Id_And, + Synth_PSL_Expression (Syn_Inst, L), + Synth_PSL_Expression (Syn_Inst, R)); end if; - return Build_Dyadic - (Build_Context, Netlists.Gates.Id_And, - Synth_PSL_Expression (Syn_Inst, L), - Synth_PSL_Expression (Syn_Inst, R)); end; when N_Or_Bool => - return Build_Dyadic + pragma Assert (Loc /= No_Location); + Res := Build_Dyadic (Build_Context, Netlists.Gates.Id_Or, Synth_PSL_Expression (Syn_Inst, Get_Left (Expr)), Synth_PSL_Expression (Syn_Inst, Get_Right (Expr))); when N_True => - return Build_Const_UB32 (Build_Context, 1, 1); + Res := Build_Const_UB32 (Build_Context, 1, 1); when N_False | N_EOS => - return Build_Const_UB32 (Build_Context, 0, 1); + Res := Build_Const_UB32 (Build_Context, 0, 1); when others => PSL.Errors.Error_Kind ("synth_psl_expr", Expr); + return No_Net; end case; + Set_Location (Res, Loc); + return Res; end Synth_PSL_Expression; function Synth_Psl_NFA (Syn_Inst : Synth_Instance_Acc; NFA : PSL.Types.PSL_NFA; Nbr_States : Int32; - States : Net) return Net + States : Net; + Loc : Source.Syn_Src) return Net is use PSL.NFAs; Ctxt : constant Context_Acc := Get_Build (Syn_Inst); @@ -2939,6 +2952,7 @@ package body Synth.Stmts is while S /= No_State loop S_Num := Get_State_Label (S); I := Build_Extract_Bit (Ctxt, States, Uns32 (S_Num)); + Set_Location (I, Loc); -- For each edge: E := Get_First_Src_Edge (S); @@ -2947,17 +2961,18 @@ package body Synth.Stmts is Cond := Build_Dyadic (Ctxt, Netlists.Gates.Id_And, I, Synth_PSL_Expression (Syn_Inst, Get_Edge_Expr (E))); + Set_Location (Cond, Loc); -- TODO: if EOS is present, then this is a live state. -- Reverse order for final concatenation. D_Num := Nbr_States - 1 - Get_State_Label (Get_Edge_Dest (E)); - if D_Arr (D_Num) = No_Net then - D_Arr (D_Num) := Cond; - else - D_Arr (D_Num) := Build_Dyadic + if D_Arr (D_Num) /= No_Net then + Cond := Build_Dyadic (Ctxt, Netlists.Gates.Id_Or, D_Arr (D_Num), Cond); + Set_Location (Cond, Loc); end if; + D_Arr (D_Num) := Cond; E := Get_Next_Src_Edge (E); end loop; @@ -2988,6 +3003,7 @@ package body Synth.Stmts is begin -- create init net, clock net Init := Build_Const_UB32 (Build_Context, 1, Uns32 (Nbr_States)); + Set_Location (Init, Stmt); Clk := Synth_PSL_Expression (Syn_Inst, Get_PSL_Clock (Stmt)); -- Check the clock is an edge and extract it. @@ -3000,11 +3016,12 @@ package body Synth.Stmts is -- build idff States := Build_Idff (Build_Context, Clk, No_Net, Init); + Set_Location (States, Stmt); -- create update nets -- For each state: if set, evaluate all outgoing edges. Next_States := - Synth_Psl_NFA (Syn_Inst, Get_PSL_NFA (Stmt), Nbr_States, States); + Synth_Psl_NFA (Syn_Inst, Get_PSL_NFA (Stmt), Nbr_States, States, Stmt); Connect (Get_Input (Get_Net_Parent (States), 1), Next_States); end Synth_Psl_Dff; @@ -3014,19 +3031,26 @@ package body Synth.Stmts is use PSL.Types; use PSL.NFAs; NFA : constant PSL_NFA := Get_PSL_NFA (Stmt); + Res : Net; begin - return Build_Extract_Bit + Res := Build_Extract_Bit (Get_Build (Syn_Inst), Next_States, Uns32 (Get_State_Label (Get_Final_State (NFA)))); + Set_Location (Res, Stmt); + return Res; end Synth_Psl_Final; function Synth_Psl_Not_Final (Syn_Inst : Synth_Instance_Acc; Stmt : Node; Next_States : Net) - return Net is + return Net + is + Res : Net; begin - return Build_Monadic + Res := Build_Monadic (Get_Build (Syn_Inst), Netlists.Gates.Id_Not, Synth_Psl_Final (Syn_Inst, Stmt, Next_States)); + Set_Location (Res, Stmt); + return Res; end Synth_Psl_Not_Final; procedure Synth_Psl_Restrict_Directive @@ -3044,6 +3068,7 @@ package body Synth.Stmts is -- The restriction holds as long as there is a 1 in the NFA state. Res := Build_Reduce (Build_Context, Netlists.Gates.Id_Red_Or, Next_States); + Set_Location (Res, Stmt); Inst := Build_Assume (Build_Context, Synth_Label (Stmt), Res); Set_Location (Inst, Get_Location (Stmt)); end if; @@ -3063,7 +3088,7 @@ package body Synth.Stmts is if Next_States /= No_Net then -- The sequence is covered as soon as the final state is reached. Res := Synth_Psl_Final (Syn_Inst, Stmt, Next_States); - Inst := Build_Cover (Build_Context, Synth_Label (Stmt), Res); + Inst := Build_Cover (Get_Build (Syn_Inst), Synth_Label (Stmt), Res); Set_Location (Inst, Get_Location (Stmt)); end if; end Synth_Psl_Cover_Directive; |