3 files changed, 2 insertions, 6 deletions
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb
index 0a752dc22..08377c1e1 100644
--- a/src/ghdldrv/ghdlsimul.adb
+++ b/src/ghdldrv/ghdlsimul.adb
@@ -13,7 +13,7 @@
 --
 --  You should have received a copy of the GNU General Public License
 --  along with this program.  If not, see <gnu.org/licenses>.
-with System; use System;
+with System;
 
 with Ada.Unchecked_Conversion;
 with Ada.Command_Line;
@@ -23,10 +23,10 @@ with Interfaces;
 with Interfaces.C;
 
 with Ghdllocal; use Ghdllocal;
-with Simple_IO; use Simple_IO;
 
 with Flags;
 with Errorout;
+with Simple_IO;
 
 with Vhdl.Nodes; use Vhdl.Nodes;
 with Vhdl.Std_Package;
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 24e79aa17..bb0aac880 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -510,7 +510,6 @@ package body Simul.Vhdl_Elab is
    procedure Gather_Process_Drivers
      (Inst : Synth_Instance_Acc; Proc : Node; Proc_Idx : Process_Index_Type)
    is
-      use Synth.Vhdl_Stmts;
       Driver_List: Iir_List;
       It : List_Iterator;
       El : Node;
@@ -537,7 +536,6 @@ package body Simul.Vhdl_Elab is
                                  Proc_Idx : Process_Index_Type;
                                  List : Iir_List)
    is
-      use Synth.Vhdl_Stmts;
       It : List_Iterator;
       El : Node;
       Sig : Sub_Signal_Type;
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index d2ed07549..0ebb719f0 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -995,7 +995,6 @@ package body Simul.Vhdl_Simul is
                                                Stmt : Node;
                                                Concurrent : Boolean)
    is
-      use Synth.Vhdl_Expr;
       Target : constant Node := Get_Target (Stmt);
       Marker : Mark_Type;
       Info : Target_Info;
@@ -1019,7 +1018,6 @@ package body Simul.Vhdl_Simul is
                                                     Stmt : Node;
                                                     Concurrent : Boolean)
    is
-      use Synth.Vhdl_Expr;
       Target : constant Node := Get_Target (Stmt);
       Marker : Mark_Type;
       Cw : Node;