diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/vhdl-ieee-numeric.adb | 18 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-numeric_std_unsigned.adb | 53 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 7 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 41 |
4 files changed, 112 insertions, 7 deletions
diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb index b165eb7e9..3a77bd0e8 100644 --- a/src/vhdl/vhdl-ieee-numeric.adb +++ b/src/vhdl/vhdl-ieee-numeric.adb @@ -626,6 +626,14 @@ package body Vhdl.Ieee.Numeric is (Type_Signed => Iir_Predefined_Ieee_Numeric_Std_Is_X_Sgn, Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_Is_X_Uns); + To_Hstring_Patterns : constant Shift_Pattern_Type := + (Type_Signed => Iir_Predefined_Ieee_Numeric_Std_To_Hstring_Sgn, + Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_To_Hstring_Uns); + + To_Ostring_Patterns : constant Shift_Pattern_Type := + (Type_Signed => Iir_Predefined_Ieee_Numeric_Std_To_Ostring_Sgn, + Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_To_Ostring_Uns); + Error : exception; procedure Extract_Declarations (Pkg_Decl : Iir_Package_Declaration; @@ -1019,10 +1027,6 @@ package body Vhdl.Ieee.Numeric is Handle_Binary (Xor_Patterns); when Name_Xnor => Handle_Binary (Xnor_Patterns); - when Name_To_Bstring - | Name_To_Ostring - | Name_To_Hstring => - null; when Name_To_Unsigned => Handle_To_Unsigned; when Name_To_Signed => @@ -1091,6 +1095,12 @@ package body Vhdl.Ieee.Numeric is Handle_To_X01 (To_Ux01_Patterns); when Name_Is_X => Handle_To_X01 (Is_X_Patterns); + when Name_To_Bstring => + null; + when Name_To_Ostring => + Handle_To_X01 (To_Ostring_Patterns); + when Name_To_Hstring => + Handle_To_X01 (To_Hstring_Patterns); when others => null; end case; diff --git a/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb b/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb index 7d8edbb96..f8c87408b 100644 --- a/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb +++ b/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb @@ -55,10 +55,59 @@ package body Vhdl.Ieee.Numeric_Std_Unsigned is Classify_Arg (Arg1, Arg1_Kind); Classify_Arg (Arg2, Arg2_Kind); case Get_Identifier (Decl) is + when Name_Op_Plus => + if Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Slv; + elsif Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Int then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Nat; + elsif Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Nat_Slv; + end if; + when Name_Op_Minus => + if Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Slv_Slv; + elsif Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Int then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Slv_Nat; + elsif Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Nat_Slv; + end if; when Name_To_Stdlogicvector => if Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Int then - Res := - Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat_Slv; + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat; + elsif Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Slv; + end if; + when Name_Resize => + if Arg2_Kind = Arg_Int then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Nat; + elsif Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Slv; + end if; + when Name_Find_Leftmost => + pragma Assert (Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Log); + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Find_Leftmost; + when Name_Find_Rightmost => + pragma Assert (Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Log); + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Find_Rightmost; + when Name_Shift_Left => + pragma Assert (Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Int); + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Shift_Left; + when Name_Shift_Right => + pragma Assert (Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Int); + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Shift_Right; + when Name_Rotate_Left => + pragma Assert (Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Int); + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Rotate_Left; + when Name_Rotate_Right => + pragma Assert (Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Int); + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Rotate_Right; + when Name_Maximum => + if Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Maximum_Slv_Slv; + end if; + when Name_Minimum => + if Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Minimum_Slv_Slv; end if; when others => null; diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index 4b98cf026..ff2d95190 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -369,6 +369,13 @@ package body Vhdl.Ieee.Std_Logic_1164 is Predefined := Iir_Predefined_Ieee_1164_To_Stdulogicvector_Bv; end if; + when Name_To_01 => + if Is_Suv_Log_Function (Decl) then + -- TODO: distinguish slv/suv. + Predefined := Iir_Predefined_Ieee_1164_To_01_Slv_Log; + elsif Is_Scalar_Scalar_Function (Decl) then + Predefined := Iir_Predefined_Ieee_1164_To_01_Log_Log; + end if; when Name_To_X01 => if Is_Vector_Function (Decl) then -- TODO: distinguish slv/suv. diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 9bf8d137d..c0d344dda 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5704,6 +5704,9 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_Condition_Operator, + Iir_Predefined_Ieee_1164_To_01_Log_Log, + Iir_Predefined_Ieee_1164_To_01_Slv_Log, + Iir_Predefined_Ieee_1164_To_Hstring, Iir_Predefined_Ieee_1164_To_Ostring, @@ -5992,6 +5995,12 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Is_X_Uns, Iir_Predefined_Ieee_Numeric_Std_Is_X_Sgn, + Iir_Predefined_Ieee_Numeric_Std_To_Hstring_Uns, + Iir_Predefined_Ieee_Numeric_Std_To_Ostring_Uns, + + Iir_Predefined_Ieee_Numeric_Std_To_Hstring_Sgn, + Iir_Predefined_Ieee_Numeric_Std_To_Ostring_Sgn, + -- numeric_bit -- To_Integer, To_Unsigned, to_Signed @@ -6003,8 +6012,33 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Bit_Tosgn_Int_Sgn_Sgn, -- Numeric_Std_Unsigned (ieee2008) + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Slv, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Nat, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Nat_Slv, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Slv_Slv, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Slv_Nat, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Nat_Slv, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Find_Rightmost, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Find_Leftmost, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Shift_Left, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Shift_Right, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Rotate_Left, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Rotate_Right, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Integer_Slv_Nat, - Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat_Slv, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Slv, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Nat, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Slv, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Maximum_Slv_Slv, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Minimum_Slv_Slv, -- Math_Real Iir_Predefined_Ieee_Math_Real_Ceil, @@ -6352,6 +6386,11 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns .. Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Sgn; + subtype Iir_Predefined_Ieee_Numeric_Std_Unsigned_Operators + is Iir_Predefined_Functions range + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Slv .. + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Nat_Slv; + -- Size of scalar types. -- Their size is determined during analysis (using the range), so that -- all backends have the same view. |