diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-oper.adb | 29 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 45 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 20 |
3 files changed, 63 insertions, 31 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 2fa4fad9c..e3fd0c714 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -398,12 +398,20 @@ package body Synth.Oper is return Value_Acc is W : constant Width := Width'Max (Left.Typ.W, Right.Typ.W); + El_Typ : Type_Acc; Rtype : Type_Acc; L1, R1 : Net; N : Net; begin if Is_Res_Vec then - Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El); + if Left.Typ.Kind = Type_Vector then + El_Typ := Left.Typ.Vec_El; + elsif Right.Typ.Kind = Type_Vector then + El_Typ := Right.Typ.Vec_El; + else + raise Internal_Error; + end if; + Rtype := Create_Vec_Type_By_Length (W, El_Typ); else Rtype := Left.Typ; end if; @@ -809,7 +817,7 @@ package body Synth.Oper is return Synth_Dyadic_Nat_Uns (Id_Add); when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv => -- "+" (Unsigned, Unsigned) @@ -826,7 +834,8 @@ package body Synth.Oper is | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv => + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv + | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv => -- "+" (Signed, Signed) return Synth_Dyadic_Sgn (Id_Add, True); @@ -836,7 +845,8 @@ package body Synth.Oper is return Synth_Dyadic_Uns_Nat (Id_Sub); when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl => + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log => -- "-" (Unsigned, Unsigned) return Synth_Dyadic_Uns (Id_Sub, True); when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int @@ -854,7 +864,9 @@ package body Synth.Oper is when Iir_Predefined_Ieee_Numeric_Std_Mul_Sgn_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv => + | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv + | Iir_Predefined_Ieee_Std_Logic_Signed_Mul_Slv_Slv => + -- "*" (Signed, Signed) declare W : constant Width := Left.Typ.W + Right.Typ.W; L, R : Net; @@ -899,7 +911,9 @@ package body Synth.Oper is end; when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns - | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv => + | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv => + -- "*" (unsigned, unsigned) declare W : constant Width := Left.Typ.W + Right.Typ.W; Rtype : Type_Acc; @@ -1125,7 +1139,8 @@ package body Synth.Oper is -- ">=" (Natural, Unsigned) [resize] return Synth_Compare_Nat_Uns (Id_Uge, Expr_Typ); when Iir_Predefined_Ieee_Numeric_Std_Ge_Uns_Nat - | Iir_Predefined_Ieee_Numeric_Std_Match_Ge_Uns_Nat => + | Iir_Predefined_Ieee_Numeric_Std_Match_Ge_Uns_Nat + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Ge_Slv_Int => -- ">=" (Unsigned, Natural) return Synth_Compare_Uns_Nat (Id_Uge, Expr_Typ); when Iir_Predefined_Ieee_Numeric_Std_Ge_Sgn_Sgn diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index 69893b954..0fcc45911 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -21,9 +21,9 @@ with Std_Names; use Std_Names; with Vhdl.Ieee.Std_Logic_1164; package body Vhdl.Ieee.Std_Logic_Unsigned is - type Arg_Kind is (Arg_Slv, Arg_Int, Arg_Sl); + type Arg_Kind is (Arg_Slv, Arg_Int, Arg_Log); type Args_Kind is (Arg_Slv_Slv, Arg_Slv_Int, Arg_Int_Slv, - Arg_Slv_Sl, Arg_Sl_Slv); + Arg_Slv_Log, Arg_Log_Slv); type Binary_Pattern_Type is array (Args_Kind) of Iir_Predefined_Functions; @@ -70,29 +70,29 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int, Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Int_Slv, - Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, - Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv); + Arg_Slv_Log => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log, + Arg_Log_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Log_Slv); Sub_Uns_Patterns : constant Binary_Pattern_Type := (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int, Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv, - Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl, - Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Sl_Slv); + Arg_Slv_Log => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log, + Arg_Log_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv); Add_Sgn_Patterns : constant Binary_Pattern_Type := (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int, Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Int_Slv, - Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Sl, - Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Sl_Slv); + Arg_Slv_Log => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Log, + Arg_Log_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Log_Slv); Sub_Sgn_Patterns : constant Binary_Pattern_Type := (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int, Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Int_Slv, - Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Sl, - Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Sl_Slv); + Arg_Slv_Log => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Log, + Arg_Log_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Log_Slv); Error : exception; @@ -106,7 +106,7 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is if Arg_Type = Vhdl.Std_Package.Integer_Subtype_Definition then Kind := Arg_Int; elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Type then - Kind := Arg_Sl; + Kind := Arg_Log; elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Vector_Type then Kind := Arg_Slv; else @@ -129,19 +129,19 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is when Arg_Slv => case Arg2_Kind is when Arg_Slv => Kind := Arg_Slv_Slv; - when Arg_Sl => Kind := Arg_Slv_Sl; + when Arg_Log => Kind := Arg_Slv_Log; when Arg_Int => Kind := Arg_Slv_Int; end case; when Arg_Int => case Arg2_Kind is when Arg_Slv => Kind := Arg_Int_Slv; - when Arg_Sl + when Arg_Log | Arg_Int => raise Error; end case; - when Arg_Sl => + when Arg_Log => case Arg2_Kind is - when Arg_Slv => Kind := Arg_Sl_Slv; - when Arg_Sl + when Arg_Slv => Kind := Arg_Log_Slv; + when Arg_Log | Arg_Int => raise Error; end case; end case; @@ -194,6 +194,19 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Res := Handle_Binary (Add_Uns_Patterns, Add_Sgn_Patterns); when Name_Op_Minus => Res := Handle_Binary (Sub_Uns_Patterns, Sub_Sgn_Patterns); + when Name_Op_Mul => + case Sign is + when Pkg_Unsigned => + pragma Assert (Arg1_Kind = Arg_Slv); + pragma Assert (Arg2_Kind = Arg_Slv); + Res := + Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv; + when Pkg_Signed => + pragma Assert (Arg1_Kind = Arg_Slv); + pragma Assert (Arg2_Kind = Arg_Slv); + Res := + Iir_Predefined_Ieee_Std_Logic_Signed_Mul_Slv_Slv; + end case; when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 56c231301..8be86f9dd 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5689,14 +5689,16 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Int_Slv, - Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, - Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Log_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv, - Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl, - Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv, + + Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Int, @@ -5728,14 +5730,16 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Signed_Add_Int_Slv, - Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Sl, - Iir_Predefined_Ieee_Std_Logic_Signed_Add_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Log, + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Log_Slv, Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Int_Slv, - Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Sl, - Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Log, + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Log_Slv, + + Iir_Predefined_Ieee_Std_Logic_Signed_Mul_Slv_Slv, -- std_logic_arith (synopsys extention). Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int, |