diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-context.adb | 24 | ||||
| -rw-r--r-- | src/synth/synth-decls.adb | 6 | ||||
| -rw-r--r-- | src/synth/synth-expr.adb | 9 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 2 | ||||
| -rw-r--r-- | src/synth/synth-values.adb | 11 | ||||
| -rw-r--r-- | src/synth/synth-values.ads | 6 |
6 files changed, 42 insertions, 16 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb index 662dfe1fe..8cbecd305 100644 --- a/src/synth/synth-context.adb +++ b/src/synth/synth-context.adb @@ -385,15 +385,22 @@ package body Synth.Context is Idx : constant Digit_Index := Digit_Index (Off / 32); Pos : constant Natural := Natural (Off mod 32); Va : Uns32; + begin + Va := Uns32 (Val.Scal); + Va := Shift_Left (Va, Pos); + Vec (Idx).Val := Vec (Idx).Val or Va; + Vec (Idx).Zx := 0; + Off := Off + 1; + end; + when Type_Logic => + declare + Idx : constant Digit_Index := Digit_Index (Off / 32); + Pos : constant Natural := Natural (Off mod 32); + Va : Uns32; Zx : Uns32; begin - if Val.Typ = Logic_Type then - From_Std_Logic (Val.Scal, Va, Zx); - Has_Zx := Has_Zx or Zx /= 0; - else - Va := Uns32 (Val.Scal); - Zx := 0; - end if; + From_Std_Logic (Val.Scal, Va, Zx); + Has_Zx := Has_Zx or Zx /= 0; Va := Shift_Left (Va, Pos); Zx := Shift_Left (Zx, Pos); Vec (Idx).Val := Vec (Idx).Val or Va; @@ -480,7 +487,8 @@ package body Synth.Context is return Val.N; when Value_Discrete => case Val.Typ.Kind is - when Type_Bit => + when Type_Bit + | Type_Logic => declare V : Logvec_Array (0 .. 0) := (0 => (0, 0)); Res : Net; diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index 3682c8781..57953ce9f 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -82,7 +82,7 @@ package body Synth.Decls is Synth_Subtype_Indication_If_Anonymous (Syn_Inst, El_Type); El_Typ := Get_Value_Type (Syn_Inst, El_Type); - if El_Typ.Kind = Type_Bit + if El_Typ.Kind in Type_Nets and then Is_One_Dimensional_Array_Type (Def) then Typ := Create_Unbounded_Vector (El_Typ); @@ -303,8 +303,8 @@ package body Synth.Decls is Rng : Discrete_Range_Type; W : Width; begin - if Btype.Kind = Type_Bit then - -- A subtype of a bit type is still a bit. + if Btype.Kind in Type_Nets then + -- A subtype of a bit/logic type is still a bit/logic. Typ := Btype; else Rng := Synth_Discrete_Range_Constraint diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 714567176..4213ea506 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -131,8 +131,10 @@ package body Synth.Expr is (Enum : Int64; Etype : Type_Acc; Val : out Uns32; Zx : out Uns32) is begin if Etype = Logic_Type then + pragma Assert (Etype.Kind = Type_Logic); From_Std_Logic (Enum, Val, Zx); elsif Etype = Boolean_Type or Etype = Bit_Type then + pragma Assert (Etype.Kind = Type_Bit); From_Bit (Enum, Val); Zx := 0; else @@ -673,7 +675,7 @@ package body Synth.Expr is Bnd := Synth_Array_Bounds (Syn_Inst, Aggr_Type, 0); pragma Assert (Bnd.Len = Uns32 (Last + 1)); - if El_Typ.Kind = Type_Bit then + if El_Typ.Kind in Type_Nets then Res_Type := Create_Vector_Type (Bnd, El_Typ); else Bnds := Create_Bound_Array (1); @@ -725,6 +727,9 @@ package body Synth.Expr is when Type_Bit => pragma Assert (Vtype.Kind = Type_Bit); return Val; + when Type_Logic => + pragma Assert (Vtype.Kind = Type_Logic); + return Val; when Type_Discrete => pragma Assert (Vtype.Kind = Type_Discrete); declare @@ -1429,7 +1434,7 @@ package body Synth.Expr is begin Bounds := Synth_Array_Bounds (Syn_Inst, Str_Type, 0); El_Type := Get_Value_Type (Syn_Inst, Get_Element_Subtype (Str_Type)); - if El_Type.Kind = Type_Bit then + if El_Type.Kind in Type_Nets then Res_Type := Create_Vector_Type (Bounds, El_Type); else Bnds := Create_Bound_Array (1); diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index b61b027ff..f2ab7cb5b 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -398,7 +398,7 @@ package body Synth.Oper is return Synth_Vec_Dyadic (Id_Xnor); when Iir_Predefined_Enum_Equality => - if Is_Bit_Type (Left_Type) then + if Left_Typ.Kind = Type_Bit then pragma Assert (Is_Bit_Type (Right_Type)); if Is_Const (Left) then return Synth_Bit_Eq_Const (Left, Right, Expr); diff --git a/src/synth/synth-values.adb b/src/synth/synth-values.adb index ed59d6af5..166bd9e43 100644 --- a/src/synth/synth-values.adb +++ b/src/synth/synth-values.adb @@ -90,6 +90,7 @@ package body Synth.Values is begin case Typ.Kind is when Type_Bit + | Type_Logic | Type_Discrete | Type_Float | Type_Vector @@ -172,6 +173,14 @@ package body Synth.Values is return To_Type_Acc (Alloc (Current_Pool, (Kind => Type_Bit, W => 1))); end Create_Bit_Type; + function Create_Logic_Type return Type_Acc + is + subtype Logic_Type_Type is Type_Type (Type_Logic); + function Alloc is new Areapools.Alloc_On_Pool_Addr (Logic_Type_Type); + begin + return To_Type_Acc (Alloc (Current_Pool, (Kind => Type_Logic, W => 1))); + end Create_Logic_Type; + function Create_Discrete_Type (Rng : Discrete_Range_Type; W : Width) return Type_Acc is @@ -587,7 +596,7 @@ package body Synth.Values is begin Instance_Pool := Global_Pool'Access; Boolean_Type := Create_Bit_Type; - Logic_Type := Create_Bit_Type; + Logic_Type := Create_Logic_Type; Bit_Type := Create_Bit_Type; end Init; end Synth.Values; diff --git a/src/synth/synth-values.ads b/src/synth/synth-values.ads index 5c5c35e97..c79e989b3 100644 --- a/src/synth/synth-values.ads +++ b/src/synth/synth-values.ads @@ -73,6 +73,7 @@ package Synth.Values is type Type_Kind is ( Type_Bit, + Type_Logic, Type_Discrete, Type_Float, Type_Vector, @@ -86,6 +87,8 @@ package Synth.Values is Type_Record ); + subtype Type_Nets is Type_Kind range Type_Bit .. Type_Logic; + type Type_Type (Kind : Type_Kind); type Type_Acc is access Type_Type; @@ -104,7 +107,8 @@ package Synth.Values is type Type_Type (Kind : Type_Kind) is record W : Width; case Kind is - when Type_Bit => + when Type_Bit + | Type_Logic => null; when Type_Discrete => Drange : Discrete_Range_Type; |