diff options
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-parse_psl.adb | 110 | ||||
| -rw-r--r-- | src/vhdl/vhdl-scanner.adb | 8 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_psl.adb | 11 | ||||
| -rw-r--r-- | src/vhdl/vhdl-tokens.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-tokens.ads | 1 |
5 files changed, 79 insertions, 53 deletions
diff --git a/src/vhdl/vhdl-parse_psl.adb b/src/vhdl/vhdl-parse_psl.adb index b664ec5c2..e50367648 100644 --- a/src/vhdl/vhdl-parse_psl.adb +++ b/src/vhdl/vhdl-parse_psl.adb @@ -679,12 +679,12 @@ package body Vhdl.Parse_Psl is begin case Get_Kind (N) is when N_Sequence_Instance - | N_Star_Repeat_Seq - | N_Plus_Repeat_Seq - | N_Equal_Repeat_Seq - | N_Goto_Repeat_Seq - | N_Braced_SERE - | N_Clocked_SERE => + | N_Star_Repeat_Seq + | N_Plus_Repeat_Seq + | N_Equal_Repeat_Seq + | N_Goto_Repeat_Seq + | N_Braced_SERE + | N_Clocked_SERE => return N; when N_And_Prop => Res := Create_Node (N_And_Seq); @@ -699,52 +699,54 @@ package body Vhdl.Parse_Psl is Set_Right (N, Property_To_Sequence (Get_Right (N))); return N; when N_Clock_Event - | N_Always - | N_Never - | N_Eventually - | N_Until - | N_Property_Parameter - | N_Property_Instance - | N_Endpoint_Instance - | N_Strong - | N_Abort - | N_Next_Event_E - | N_Next_Event_A - | N_Next_Event - | N_Next_E - | N_Next_A - | N_Next - | N_Log_Imp_Prop - | N_Paren_Prop => + | N_Always + | N_Never + | N_Eventually + | N_Until + | N_Property_Parameter + | N_Property_Instance + | N_Endpoint_Instance + | N_Strong + | N_Abort + | N_Next_Event_E + | N_Next_Event_A + | N_Next_Event + | N_Next_E + | N_Next_A + | N_Next + | N_Log_Imp_Prop + | N_Log_Equiv_Prop + | N_Paren_Prop => Error_Msg_Parse (+N, "construct not allowed in sequences"); return N; when N_Const_Parameter - | N_Boolean_Parameter - | N_Sequence_Parameter - | N_Actual - | N_And_Seq - | N_Or_Seq - | N_Imp_Seq - | N_Overlap_Imp_Seq - | N_Match_And_Seq - | N_Imp_Bool - | N_Or_Bool - | N_And_Bool - | N_Not_Bool - | N_Paren_Bool - | N_Fusion_SERE - | N_HDL_Expr - | N_HDL_Bool - | N_Hdl_Mod_Name - | N_Concat_SERE - | N_Within_SERE - | N_False - | N_True - | N_Number - | N_Name_Decl - | N_Name - | N_EOS - | N_Error => + | N_Boolean_Parameter + | N_Sequence_Parameter + | N_Actual + | N_And_Seq + | N_Or_Seq + | N_Imp_Seq + | N_Equiv_Bool + | N_Overlap_Imp_Seq + | N_Match_And_Seq + | N_Imp_Bool + | N_Or_Bool + | N_And_Bool + | N_Not_Bool + | N_Paren_Bool + | N_Fusion_SERE + | N_HDL_Expr + | N_HDL_Bool + | N_Hdl_Mod_Name + | N_Concat_SERE + | N_Within_SERE + | N_False + | N_True + | N_Number + | N_Name_Decl + | N_Name + | N_EOS + | N_Error => return N; when N_Vmode | N_Vunit @@ -812,6 +814,7 @@ package body Vhdl.Parse_Psl is loop case Current_Token is when Tok_Minus_Greater => + -- -> if Prio > Prio_Bool_Imp then return Res; end if; @@ -820,6 +823,15 @@ package body Vhdl.Parse_Psl is Scan; Set_Right (N, Parse_FL_Property (Prio_Bool_Imp)); Res := N; + when Tok_Equiv_Arrow => + if Prio > Prio_Bool_Imp then + return Res; + end if; + N := Create_Node_Loc (N_Log_Equiv_Prop); + Set_Left (N, Res); + Scan; + Set_Right (N, Parse_FL_Property (Prio_Bool_Imp)); + Res := N; when Tok_Bar_Arrow => if Prio > Prio_Seq_Imp then return Res; diff --git a/src/vhdl/vhdl-scanner.adb b/src/vhdl/vhdl-scanner.adb index bdda2340f..fba0dab54 100644 --- a/src/vhdl/vhdl-scanner.adb +++ b/src/vhdl/vhdl-scanner.adb @@ -2257,6 +2257,14 @@ package body Vhdl.Scanner is when '<' => Current_Token := Tok_Double_Less; Pos := Pos + 2; + when '-' => + if Flag_Psl and then Source (Pos + 2) = '>' then + Current_Token := Tok_Equiv_Arrow; + Pos := Pos + 3; + else + Current_Token := Tok_Less; + Pos := Pos + 1; + end if; when others => Current_Token := Tok_Less; Pos := Pos + 1; diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index e4b3554fd..0e077b8c9 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -552,7 +552,7 @@ package body Vhdl.Sem_Psl is when N_Braced_SERE => return Sem_Sequence (Prop); when N_Always - | N_Never => + | N_Never => -- By extension, clock_event is allowed within outermost -- always/never. Sem_Property (Prop, Top); @@ -572,15 +572,16 @@ package body Vhdl.Sem_Psl is Sem_Boolean (Prop); return Prop; when N_Until - | N_Before => + | N_Before => Res := Sem_Property (Get_Left (Prop)); Set_Left (Prop, Res); Res := Sem_Property (Get_Right (Prop)); Set_Right (Prop, Res); return Prop; when N_Log_Imp_Prop - | N_And_Prop - | N_Or_Prop => + | N_Log_Equiv_Prop + | N_And_Prop + | N_Or_Prop => declare L, R : PSL_Node; begin @@ -598,6 +599,8 @@ package body Vhdl.Sem_Psl is return Reduce_Logic_Binary_Node (Prop, N_Or_Bool); when N_Log_Imp_Prop => return Reduce_Logic_Binary_Node (Prop, N_Imp_Bool); + when N_Log_Equiv_Prop => + return Reduce_Logic_Binary_Node (Prop, N_Equiv_Bool); when others => Error_Kind ("psl.sem_property(log)", Prop); end case; diff --git a/src/vhdl/vhdl-tokens.adb b/src/vhdl/vhdl-tokens.adb index 0242808bf..c4550af82 100644 --- a/src/vhdl/vhdl-tokens.adb +++ b/src/vhdl/vhdl-tokens.adb @@ -430,6 +430,8 @@ package body Vhdl.Tokens is return "|=>"; when Tok_Minus_Greater => return "->"; + when Tok_Equiv_Arrow => + return "<->"; when Tok_Arobase => return "@"; diff --git a/src/vhdl/vhdl-tokens.ads b/src/vhdl/vhdl-tokens.ads index e35a3a4e4..373b92acc 100644 --- a/src/vhdl/vhdl-tokens.ads +++ b/src/vhdl/vhdl-tokens.ads @@ -100,6 +100,7 @@ package Vhdl.Tokens is Tok_Bar_Arrow, -- |-> Tok_Bar_Double_Arrow, -- |=> Tok_Minus_Greater, -- -> + Tok_Equiv_Arrow, -- <-> Tok_Arobase, -- @ -- multiplying operator |