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-rw-r--r--src/vhdl/vhdl-ieee-std_logic_unsigned.adb5
-rw-r--r--src/vhdl/vhdl-nodes.ads2
2 files changed, 7 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb
index 9e2bb5269..c3b30be8e 100644
--- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb
@@ -184,6 +184,11 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is
else
-- Monadic function.
case Get_Identifier (Decl) is
+ when Name_Conv_Integer =>
+ if Sign = Pkg_Unsigned then
+ Res :=
+ Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer;
+ end if;
when others =>
null;
end case;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index bd25fb805..8de95478b 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -5093,6 +5093,8 @@ package Vhdl.Nodes is
Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Int,
Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Int_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer,
+
-- Std_Logic_Signed (synopsys extension).
Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv,
Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int,