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Diffstat (limited to 'src/vhdl')
-rw-r--r-- | src/vhdl/translate/trans-chap8.adb | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/vhdl/translate/trans-chap8.adb b/src/vhdl/translate/trans-chap8.adb index 5d662f410..1e7bb1956 100644 --- a/src/vhdl/translate/trans-chap8.adb +++ b/src/vhdl/translate/trans-chap8.adb @@ -2594,6 +2594,16 @@ package body Trans.Chap8 is Act_Type := Get_Type (Actual); end case; + -- If the actual is a slice, create the type early so that they + -- could be used in different states. If they are created too + -- late, they could be created in a state but referenced in + -- a different one. + if Actual /= Null_Iir + and then Get_Kind (Actual) = Iir_Kind_Slice_Name + then + Chap3.Create_Composite_Subtype (Act_Type, False); + end if; + -- For out or inout scalar variable, create a field for the -- actual value. if Actual /= Null_Iir |