4 files changed, 36 insertions, 18 deletions

diff --git a/src/vhdl/translate/trans-chap1.adb b/src/vhdl/translate/trans-chap1.adb
index ff72300ef..b9f00ddee 100644
--- a/src/vhdl/translate/trans-chap1.adb
+++ b/src/vhdl/translate/trans-chap1.adb
@@ -90,7 +90,7 @@ package body Trans.Chap1 is
             end if;
             Chap5.Elab_Unconstrained_Port_Bounds (El, Default);
          end if;
-         Chap4.Elab_Signal_Declaration_Storage (El);
+         Chap4.Elab_Signal_Declaration_Storage (El, False);
          Chap4.Elab_Signal_Declaration_Object (El, Entity, False);
          Close_Temp;
 
diff --git a/src/vhdl/translate/trans-chap4.adb b/src/vhdl/translate/trans-chap4.adb
index 735464ce4..8469e1cca 100644
--- a/src/vhdl/translate/trans-chap4.adb
+++ b/src/vhdl/translate/trans-chap4.adb
@@ -1006,7 +1006,7 @@ package body Trans.Chap4 is
       Finish_Data_Record => Elab_Signal_Finish_Composite);
 
    --  Elaborate signal subtypes and allocate the storage for the object.
-   procedure Elab_Signal_Declaration_Storage (Decl : Iir)
+   procedure Elab_Signal_Declaration_Storage (Decl : Iir; Has_Copy : Boolean)
    is
       Sig_Type  : constant Iir := Get_Type (Decl);
       Type_Info : Type_Info_Acc;
@@ -1023,23 +1023,37 @@ package body Trans.Chap4 is
       if Type_Info.Type_Mode = Type_Mode_Fat_Array then
          --  Unbounded types are only allowed for ports; in that case the
          --  bounds have already been set.
-         Chap6.Translate_Signal_Name (Decl, Name_Sig, Name_Val);
+         if Has_Copy then
+            Name_Sig := Chap6.Translate_Name (Decl, Mode_Signal);
+         else
+            Chap6.Translate_Signal_Name (Decl, Name_Sig, Name_Val);
+         end if;
          Name_Sig := Stabilize (Name_Sig);
          Chap3.Allocate_Fat_Array_Base (Alloc_System, Name_Sig, Sig_Type);
-         Name_Val := Stabilize (Name_Val);
-         Chap3.Allocate_Fat_Array_Base (Alloc_System, Name_Val, Sig_Type);
+         if not Has_Copy then
+            Name_Val := Stabilize (Name_Val);
+            Chap3.Allocate_Fat_Array_Base (Alloc_System, Name_Val, Sig_Type);
+         end if;
       elsif Is_Complex_Type (Type_Info) then
-         Chap6.Translate_Signal_Name (Decl, Name_Sig, Name_Val);
+         if Has_Copy then
+            Name_Sig := Chap6.Translate_Name (Decl, Mode_Signal);
+         else
+            Chap6.Translate_Signal_Name (Decl, Name_Sig, Name_Val);
+         end if;
          Allocate_Complex_Object (Sig_Type, Alloc_System, Name_Sig);
-         Allocate_Complex_Object (Sig_Type, Alloc_System, Name_Val);
+         if not Has_Copy then
+            Allocate_Complex_Object (Sig_Type, Alloc_System, Name_Val);
+         end if;
       elsif Get_Kind (Decl) = Iir_Kind_Interface_Signal_Declaration then
-         --  A port that isn't collapsed.  Allocate value.
-         Name_Val := Chap6.Translate_Name (Decl, Mode_Value);
-         New_Assign_Stmt
-           (M2Lp (Name_Val),
-            Gen_Alloc (Alloc_System,
-                       Chap3.Get_Object_Size (Name_Val, Sig_Type),
-                       Type_Info.Ortho_Ptr_Type (Mode_Value)));
+         if not Has_Copy then
+            --  A port that isn't collapsed.  Allocate value.
+            Name_Val := Chap6.Translate_Name (Decl, Mode_Value);
+            New_Assign_Stmt
+              (M2Lp (Name_Val),
+               Gen_Alloc (Alloc_System,
+                          Chap3.Get_Object_Size (Name_Val, Sig_Type),
+                          Type_Info.Ortho_Ptr_Type (Mode_Value)));
+         end if;
       end if;
 
       Close_Temp;
@@ -1153,7 +1167,7 @@ package body Trans.Chap4 is
      (Decl : Iir; Parent : Iir; Check_Null : Boolean)
    is
    begin
-      Elab_Signal_Declaration_Storage (Decl);
+      Elab_Signal_Declaration_Storage (Decl, False);
       Elab_Signal_Declaration_Object (Decl, Parent, Check_Null);
    end Elab_Signal_Declaration;
 
diff --git a/src/vhdl/translate/trans-chap4.ads b/src/vhdl/translate/trans-chap4.ads
index 317d10342..d91f0ee52 100644
--- a/src/vhdl/translate/trans-chap4.ads
+++ b/src/vhdl/translate/trans-chap4.ads
@@ -68,7 +68,10 @@ package Trans.Chap4 is
    procedure Translate_Generic_Chain (Parent : Iir);
 
    --  Elaborate signal subtypes and allocate the storage for the object.
-   procedure Elab_Signal_Declaration_Storage (Decl : Iir);
+   --  If HAS_COPY is true, do not allocate storage for values, as the values
+   --  will be directly referenced from the association.
+   procedure Elab_Signal_Declaration_Storage
+     (Decl : Iir; Has_Copy : Boolean);
 
    --  Create signal object.
    --  Note: SIG can be a signal sub-element (used when signals are
diff --git a/src/vhdl/translate/trans-chap5.adb b/src/vhdl/translate/trans-chap5.adb
index f52de48be..a0c90ba6f 100644
--- a/src/vhdl/translate/trans-chap5.adb
+++ b/src/vhdl/translate/trans-chap5.adb
@@ -723,10 +723,11 @@ package body Trans.Chap5 is
                when Iir_Kind_Association_Element_By_Individual
                  | Iir_Kind_Association_Element_Open =>
                   pragma Assert (Get_Whole_Association_Flag (Assoc));
-                  Chap4.Elab_Signal_Declaration_Storage (Formal);
+                  Chap4.Elab_Signal_Declaration_Storage (Formal, False);
                when Iir_Kind_Association_Element_By_Expression =>
                   if Get_Whole_Association_Flag (Assoc) then
-                     Chap4.Elab_Signal_Declaration_Storage (Formal);
+                     Chap4.Elab_Signal_Declaration_Storage
+                       (Formal, Get_Collapse_Signal_Flag (Assoc));
                   end if;
             end case;
             Close_Temp;