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-rw-r--r--src/std_names.adb321
1 files changed, 216 insertions, 105 deletions
diff --git a/src/std_names.adb b/src/std_names.adb
index dfe322136..74abf7815 100644
--- a/src/std_names.adb
+++ b/src/std_names.adb
@@ -169,6 +169,189 @@ package body Std_Names is
Def ("through", Name_Through);
Def ("tolerance", Name_Tolerance);
+ -- Verilog keywords
+ Def ("always", Name_Always);
+ Def ("assign", Name_Assign);
+ Def ("buf", Name_Buf);
+ Def ("bufif0", Name_Bufif0);
+ Def ("bufif1", Name_Bufif1);
+ Def ("casex", Name_Casex);
+ Def ("casez", Name_Casez);
+ Def ("cmos", Name_Cmos);
+ Def ("deassign", Name_Deassign);
+ Def ("default", Name_Default);
+ Def ("defparam", Name_Defparam);
+ Def ("disable", Name_Disable);
+ Def ("edge", Name_Edge);
+ Def ("endcase", Name_Endcase);
+ Def ("endfunction", Name_Endfunction);
+ Def ("endmodule", Name_Endmodule);
+ Def ("endprimitive", Name_Endprimitive);
+ Def ("endspecify", Name_Endspecify);
+ Def ("endtable", Name_Endtable);
+ Def ("endtask", Name_Endtask);
+ Def ("force", Name_Force);
+ Def ("forever", Name_Forever);
+ Def ("fork", Name_Fork);
+ Def ("highz0", Name_Highz0);
+ Def ("highz1", Name_Highz1);
+ Def ("ifnone", Name_Ifnone);
+ Def ("initial", Name_Initial);
+ Def ("input", Name_Input);
+ Def ("join", Name_Join);
+ Def ("large", Name_Large);
+ Def ("macromodule", Name_Macromodule);
+ Def ("medium", Name_Medium);
+ Def ("module", Name_Module);
+ Def ("negedge", Name_Negedge);
+ Def ("nmos", Name_Nmos);
+ Def ("notif0", Name_Notif0);
+ Def ("notif1", Name_Notif1);
+ Def ("output", Name_Output);
+ Def ("pmos", Name_Pmos);
+ Def ("posedge", Name_Posedge);
+ Def ("primitive", Name_Primitive);
+ Def ("pull0", Name_Pull0);
+ Def ("pull1", Name_Pull1);
+ Def ("pulldown", Name_Pulldown);
+ Def ("pullup", Name_Pullup);
+ Def ("realtime", Name_Realtime);
+ Def ("release", Name_Release);
+ Def ("reg", Name_Reg);
+ Def ("repeat", Name_Repeat);
+ Def ("rcmos", Name_Rcmos);
+ Def ("rnmos", Name_Rnmos);
+ Def ("rpmos", Name_Rpmos);
+ Def ("rtran", Name_Rtran);
+ Def ("rtranif0", Name_Rtranif0);
+ Def ("rtranif1", Name_Rtranif1);
+ Def ("scalared", Name_Scalared);
+ Def ("small", Name_Small);
+ Def ("specify", Name_Specify);
+ Def ("specparam", Name_Specparam);
+ Def ("strong0", Name_Strong0);
+ Def ("strong1", Name_Strong1);
+ Def ("supply0", Name_Supply0);
+ Def ("supply1", Name_Supply1);
+ Def ("table", Name_Tablex);
+ Def ("task", Name_Task);
+ Def ("tran", Name_Tran);
+ Def ("tranif0", Name_Tranif0);
+ Def ("tranif1", Name_Tranif1);
+ Def ("tri", Name_Tri);
+ Def ("tri0", Name_Tri0);
+ Def ("tri1", Name_Tri1);
+ Def ("triand", Name_Triand);
+ Def ("trior", Name_Trior);
+ Def ("trireg", Name_Trireg);
+ Def ("vectored", Name_Vectored);
+ Def ("wand", Name_Wand);
+ Def ("weak0", Name_Weak0);
+ Def ("weak1", Name_Weak1);
+ Def ("wire", Name_Wire);
+ Def ("wor", Name_Wor);
+
+ -- Verilog 2001
+ Def ("automatic", Name_Automatic);
+ Def ("endgenerate", Name_Endgenerate);
+ Def ("genvar", Name_Genvar);
+ Def ("localparam", Name_Localparam);
+ Def ("unsigned", Name_Unsigned);
+ Def ("signed", Name_Signed);
+
+ -- Verilog 2005
+ Def ("uwire", Name_Uwire);
+
+ -- SystemVerilog 2005
+ Def ("always_comb", Name_Always_Comb);
+ Def ("always_ff", Name_Always_Ff);
+ Def ("always_latch", Name_Always_Latch);
+ Def ("bit", Name_Bit);
+ Def ("byte", Name_Byte);
+ Def ("changed", Name_Changed);
+ Def ("char", Name_Char);
+ Def ("const", Name_Const);
+ Def ("continue", Name_Continue);
+ Def ("do", Name_Do);
+ Def ("endinterface", Name_Endinterface);
+ Def ("endtransition", Name_Endtransition);
+ Def ("enum", Name_Enum);
+ Def ("export", Name_Export);
+ Def ("extern", Name_Extern);
+ Def ("forkjoin", Name_Forkjoin);
+ Def ("iff", Name_Iff);
+ Def ("import", Name_Import);
+ Def ("int", Name_Int);
+ Def ("interface", Name_Interface);
+ Def ("logic", Name_Logic);
+ Def ("longint", Name_Longint);
+ Def ("longreal", Name_Longreal);
+ Def ("modport", Name_Modport);
+ Def ("packed", Name_Packed);
+ Def ("priority", Name_Priority);
+ Def ("shortint", Name_Shortint);
+ Def ("shortreal", Name_Shortreal);
+ Def ("static", Name_Static);
+ Def ("struct", Name_Struct);
+ Def ("timeprecision", Name_Timeprecision);
+ Def ("timeunit", Name_Timeunit);
+ Def ("transition", Name_Transition);
+ Def ("typedef", Name_Typedef);
+ Def ("union", Name_Union);
+ Def ("unique", Name_Unique);
+ Def ("void", Name_Void);
+
+ -- SystemVerilog 3.1
+ Def ("chandle", Name_Chandle);
+ Def ("class", Name_Class);
+ Def ("clocking", Name_Clocking);
+ Def ("constraint", Name_Constraint);
+ Def ("cover", Name_Cover);
+ Def ("dist", Name_Dist);
+ Def ("endclass", Name_Endclass);
+ Def ("endclocking", Name_Endclocking);
+ Def ("endprogram", Name_Endprogram);
+ Def ("endproperty", Name_Endproperty);
+ Def ("endsequence", Name_Endsequence);
+ Def ("extends", Name_Extends);
+ Def ("final", Name_Final);
+ Def ("first_match", Name_First_Match);
+ Def ("inside", Name_Inside);
+ Def ("intersect", Name_Intersect);
+ Def ("join_any", Name_Join_Any);
+ Def ("join_none", Name_Join_None);
+ Def ("local", Name_Local);
+ Def ("program", Name_Program);
+ Def ("property", Name_Property);
+ Def ("rand", Name_Rand);
+ Def ("randc", Name_Randc);
+ Def ("ref", Name_Ref);
+ Def ("sequence", Name_Sequence);
+ Def ("solve", Name_Solve);
+ Def ("string", Name_String);
+ Def ("super", Name_Super);
+ Def ("this", Name_This);
+ Def ("throughout", Name_Throughout);
+ Def ("var", Name_Var);
+ Def ("virtual", Name_Virtual);
+ Def ("wait_order", Name_Wait_Order);
+
+ -- SystemVerilog 3.1a
+ Def ("assume", Name_Assume);
+ Def ("covergroup", Name_Covergroup);
+ Def ("coverpoint", Name_Coverpoint);
+ Def ("endgroup", Name_Endgroup);
+ Def ("endpackage", Name_Endpackage);
+ Def ("expect", Name_Expect);
+ Def ("foreach", Name_Foreach);
+ Def ("ingore_bins", Name_Ignore_Bins);
+ Def ("illegal_bins", Name_Illegal_Bins);
+ Def ("matches", Name_Matches);
+ Def ("randcase", Name_Randcase);
+ Def ("randsequence", Name_Randsequence);
+ Def ("tagged", Name_Tagged);
+ Def ("wildcard", Name_Wildcard);
+
-- Create operators.
Def ("=", Name_Op_Equality);
Def ("/=", Name_Op_Inequality);
@@ -381,9 +564,11 @@ package body Std_Names is
Def ("write", Name_Write);
Def ("flush", Name_Flush);
Def ("endfile", Name_Endfile);
- Def ("p", Name_P);
+ Def ("i", Name_I);
+ Def ("j", Name_J);
Def ("f", Name_F);
Def ("l", Name_L);
+ Def ("p", Name_P);
Def ("r", Name_R);
Def ("s", Name_S);
Def ("v", Name_V);
@@ -403,6 +588,10 @@ package body Std_Names is
Def ("textio_write_real", Name_Textio_Write_Real);
Def ("get_resolution_limit", Name_Get_Resolution_Limit);
Def ("control_simulation", Name_Control_Simulation);
+ Def ("step", Name_Step);
+ Def ("index", Name_Index);
+ Def ("__FILE__", Name_Uu_File_Uu);
+ Def ("__LINE__", Name_Uu_Line_Uu);
Def ("ieee", Name_Ieee);
Def ("std_logic_1164", Name_Std_Logic_1164);
@@ -424,103 +613,38 @@ package body Std_Names is
Def ("std_logic_textio", Name_Std_Logic_Textio);
Def ("std_logic_unsigned", Name_Std_Logic_Unsigned);
- -- Verilog keywords
- Def ("always", Name_Always);
- Def ("assign", Name_Assign);
- Def ("buf", Name_Buf);
- Def ("bufif0", Name_Bufif0);
- Def ("bufif1", Name_Bufif1);
- Def ("casex", Name_Casex);
- Def ("casez", Name_Casez);
- Def ("cmos", Name_Cmos);
- Def ("deassign", Name_Deassign);
- Def ("default", Name_Default);
- Def ("defparam", Name_Defparam);
- Def ("disable", Name_Disable);
- Def ("endcase", Name_Endcase);
- Def ("endfunction", Name_Endfunction);
- Def ("endmodule", Name_Endmodule);
- Def ("endprimitive", Name_Endprimitive);
- Def ("endspecify", Name_Endspecify);
- Def ("endtable", Name_Endtable);
- Def ("endtask", Name_Endtask);
- Def ("forever", Name_Forever);
- Def ("fork", Name_Fork);
- Def ("highz0", Name_Highz0);
- Def ("highz1", Name_Highz1);
- Def ("initial", Name_Initial);
- Def ("input", Name_Input);
- Def ("join", Name_Join);
- Def ("large", Name_Large);
- Def ("medium", Name_Medium);
- Def ("module", Name_Module);
- Def ("negedge", Name_Negedge);
- Def ("nmos", Name_Nmos);
- Def ("notif0", Name_Notif0);
- Def ("notif1", Name_Notif1);
- Def ("output", Name_Output);
- Def ("pmos", Name_Pmos);
- Def ("posedge", Name_Posedge);
- Def ("primitive", Name_Primitive);
- Def ("pull0", Name_Pull0);
- Def ("pull1", Name_Pull1);
- Def ("pulldown", Name_Pulldown);
- Def ("pullup", Name_Pullup);
- Def ("reg", Name_Reg);
- Def ("repeat", Name_Repeat);
- Def ("rcmos", Name_Rcmos);
- Def ("rnmos", Name_Rnmos);
- Def ("rpmos", Name_Rpmos);
- Def ("rtran", Name_Rtran);
- Def ("rtranif0", Name_Rtranif0);
- Def ("rtranif1", Name_Rtranif1);
- Def ("small", Name_Small);
- Def ("specify", Name_Specify);
- Def ("specparam", Name_Specparam);
- Def ("strong0", Name_Strong0);
- Def ("strong1", Name_Strong1);
- Def ("supply0", Name_Supply0);
- Def ("supply1", Name_Supply1);
- Def ("table", Name_Tablex);
- Def ("task", Name_Task);
- Def ("tran", Name_Tran);
- Def ("tranif0", Name_Tranif0);
- Def ("tranif1", Name_Tranif1);
- Def ("tri", Name_Tri);
- Def ("tri0", Name_Tri0);
- Def ("tri1", Name_Tri1);
- Def ("triand", Name_Triand);
- Def ("trior", Name_Trior);
- Def ("trireg", Name_Trireg);
- Def ("wand", Name_Wand);
- Def ("weak0", Name_Weak0);
- Def ("weak1", Name_Weak1);
- Def ("wire", Name_Wire);
- Def ("wor", Name_Wor);
-
- -- Verilog 2001
- Def ("automatic", Name_Automatic);
- Def ("endgenerate", Name_Endgenerate);
- Def ("genvar", Name_Genvar);
- Def ("localparam", Name_Localparam);
- Def ("unsigned", Name_Unsigned);
- Def ("signed", Name_Signed);
-
- Def ("define", Name_Define);
- Def ("endif", Name_Endif);
- Def ("ifdef", Name_Ifdef);
- Def ("include", Name_Include);
- Def ("timescale", Name_Timescale);
- Def ("undef", Name_Undef);
- Def ("protect", Name_Protect);
+ -- Verilog directives
+ Def ("define", Name_Define);
+ Def ("endif", Name_Endif);
+ Def ("ifdef", Name_Ifdef);
+ Def ("ifndef", Name_Ifndef);
+ Def ("include", Name_Include);
+ Def ("timescale", Name_Timescale);
+ Def ("undef", Name_Undef);
+ Def ("protect", Name_Protect);
Def ("begin_protected", Name_Begin_Protected);
Def ("end_protected", Name_End_Protected);
Def ("key_block", Name_Key_Block);
Def ("data_block", Name_Data_Block);
+ Def ("line", Name_Line);
-- Verilog system tasks
- Def ("display", Name_Display);
- Def ("finish", Name_Finish);
+ Def ("$bits", Name_D_Bits);
+ Def ("$root", Name_D_Root);
+ Def ("$unit", Name_D_Unit);
+
+ -- SV methods.
+ Def ("size", Name_Size);
+ Def ("insert", Name_Insert);
+ Def ("delete", Name_Delete);
+ Def ("pop_front", Name_Pop_Front);
+ Def ("pop_back", Name_Pop_Back);
+ Def ("push_front", Name_Push_Front);
+ Def ("push_back", Name_Push_Back);
+ Def ("name", Name_Name);
+ Def ("len", Name_Len);
+ Def ("substr", Name_Substr);
+ Def ("exists", Name_Exists);
-- BSV keywords
Def ("Action", Name_uAction);
@@ -537,32 +661,24 @@ package body Std_Names is
Def ("endactionvalue", Name_Endactionvalue);
Def ("ancestor", Name_Ancestor);
Def ("clocked_by", Name_Clocked_By);
- Def ("continue", Name_Continue);
Def ("default_clock", Name_Default_Clock);
Def ("default_reset", Name_Default_Reset);
Def ("dependencies", Name_Dependencies);
Def ("deriving", Name_Deriving);
Def ("determines", Name_Determines);
Def ("enable", Name_Enable);
- Def ("enum", Name_Enum);
- Def ("export", Name_Export);
Def ("ifc_inout", Name_Ifc_Inout);
- Def ("import", Name_Import);
Def ("input_clock", Name_Input_Clock);
Def ("input_reset", Name_Input_Reset);
Def ("instance", Name_Instance);
Def ("endinstance", Name_Endinstance);
- Def ("interface", Name_Interface);
- Def ("endinterface", Name_Endinterface);
Def ("let", Name_Let);
Def ("match", Name_Match);
- Def ("matches", Name_Matches);
Def ("method", Name_Method);
Def ("endmethod", Name_Endmethod);
Def ("numeric", Name_Numeric);
Def ("output_clock", Name_Output_Clock);
Def ("output_reset", Name_Output_Reset);
- Def ("endpackage", Name_Endpackage);
Def ("par", Name_Par);
Def ("endpar", Name_Endpar);
Def ("path", Name_Path);
@@ -577,15 +693,10 @@ package body Std_Names is
Def ("schedule", Name_Schedule);
Def ("seq", Name_Seq);
Def ("endseq", Name_Endseq);
- Def ("struct", Name_Struct);
- Def ("tagged", Name_Tagged);
Def ("typeclass", Name_Typeclass);
Def ("endtypeclass", Name_Endtypeclass);
- Def ("typedef", Name_Typedef);
- Def ("union", Name_Union);
Def ("valueof", Name_Valueof);
Def ("valueOf", Name_uValueof);
- Def ("void", Name_Void);
-- VHDL special comments
Def ("psl", Name_Psl);
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-15 22:33:30 +0000