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Diffstat (limited to 'pyGHDL/dom/DesignUnit.py')
| -rw-r--r-- | pyGHDL/dom/DesignUnit.py | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 331b2526a..40fc6796a 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -33,10 +33,10 @@ # ============================================================================ # """ -This module contains all DOM classes for VHDL's design units (:cls:`entity <Entity>`, -:cls:`architecture <Architecture>`, :cls:`package <Package>`, -:cls:`package body <PackageBody>`, :cls:`context <Context>` and -:cls:`configuration <Configuration>`. +This module contains all DOM classes for VHDL's design units (:class:`entity <Entity>`, +:class:`architecture <Architecture>`, :class:`package <Package>`, +:class:`package body <PackageBody>`, :class:`context <Context>` and +:class:`configuration <Configuration>`. """ @@ -58,7 +58,6 @@ from pyGHDL.dom.InterfaceItem import GenericConstantInterfaceItem, PortSignalInt __all__ = [] - @export class Entity(VHDLModel_Entity, GHDLMixin): |