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-rw-r--r--doc/using/UART_srcs/tx/BlockTX.pngbin0 -> 21655 bytes
-rw-r--r--doc/using/UART_srcs/tx/TX.ghwbin0 -> 349969 bytes
-rw-r--r--doc/using/UART_srcs/tx/TX.svg395
-rw-r--r--doc/using/UART_srcs/tx/TX_simple.pngbin0 -> 63700 bytes
-rw-r--r--doc/using/UART_srcs/tx/UART_TX_8N1.vhd162
-rw-r--r--doc/using/UART_srcs/tx/makefile8
-rw-r--r--doc/using/UART_srcs/tx/path6054.pngbin0 -> 74166 bytes
-rw-r--r--doc/using/UART_srcs/tx/tb_UART_TX_8N1.vhd95
-rw-r--r--doc/using/UART_srcs/tx/tx.gtkw33
9 files changed, 693 insertions, 0 deletions
diff --git a/doc/using/UART_srcs/tx/BlockTX.png b/doc/using/UART_srcs/tx/BlockTX.png
new file mode 100644
index 000000000..9031bb2f3
--- /dev/null
+++ b/doc/using/UART_srcs/tx/BlockTX.png
Binary files differ
diff --git a/doc/using/UART_srcs/tx/TX.ghw b/doc/using/UART_srcs/tx/TX.ghw
new file mode 100644
index 000000000..1af3cfed0
--- /dev/null
+++ b/doc/using/UART_srcs/tx/TX.ghw
Binary files differ
diff --git a/doc/using/UART_srcs/tx/TX.svg b/doc/using/UART_srcs/tx/TX.svg
new file mode 100644
index 000000000..35040d850
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diff --git a/doc/using/UART_srcs/tx/TX_simple.png b/doc/using/UART_srcs/tx/TX_simple.png
new file mode 100644
index 000000000..cdf10e0c6
--- /dev/null
+++ b/doc/using/UART_srcs/tx/TX_simple.png
Binary files differ
diff --git a/doc/using/UART_srcs/tx/UART_TX_8N1.vhd b/doc/using/UART_srcs/tx/UART_TX_8N1.vhd
new file mode 100644
index 000000000..c8fd80b4a
--- /dev/null
+++ b/doc/using/UART_srcs/tx/UART_TX_8N1.vhd
@@ -0,0 +1,162 @@
+-- UART_TX_8N1.vhd
+----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+--UART transmiter without parity
+
+entity UART_8N1_TX is
+ generic(
+ clk_freq : integer;
+ baudrate : integer;
+ addr_depth : integer:=5);
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ --8bit interface
+ wdata : in std_logic_vector(7 downto 0);
+ wr : in std_logic;
+ wr_en : out std_logic;
+
+ --physical wire
+ tx : out std_logic);
+end;
+
+
+architecture Behavioral of UART_8N1_TX is
+--FSM
+ type state_type is (idle, start, data0, data1, data2, data3, data4,
+ data5, data6, data7, stop);
+
+ signal state : state_type := idle;
+ signal nextstate : state_type := idle;
+
+ --FIFO
+ type RAM is array (0 to (2**(addr_depth)-1)) of std_logic_vector (7 downto 0);
+ signal fifo : RAM;
+ signal nextwrite : unsigned((addr_depth-1) downto 0);
+ signal nextread : unsigned((addr_depth-1) downto 0);
+
+ signal send_empty: std_logic;
+
+ --output
+ signal data_tx : std_logic_vector (7 downto 0);
+ constant tick : integer := (clk_freq/baudrate);
+ signal tick_counter : integer range 0 to (tick+1);
+
+begin
+
+ wr_en <= '0' when (nextwrite+1 = nextread) else '1';
+ send_empty<='1' when nextwrite=nextread else '0';
+
+ process(clk)
+ begin
+ if rising_edge(clk) then
+ if reset = '1' then
+ nextread <= (others => '0');
+ elsif state = stop and nextstate = idle then
+ nextread <= nextread+1;
+ end if;
+ end if;
+ end process;
+
+ process(clk)
+ begin
+ if rising_edge(clk) then
+ state <= nextstate;
+ end if;
+ end process;
+
+ process(clk)
+ begin
+ if rising_edge(clk) then
+ if reset = '1' then
+ nextwrite <= (others => '0');
+ elsif wr = '1' then
+ fifo(to_integer(nextwrite)) <= wdata;
+ nextwrite <= nextwrite+1;
+
+ end if;
+ end if;
+ end process;
+
+
+ data_tx <= fifo(to_integer(nextread));
+
+ process(clk)
+ begin
+ if rising_edge(clk) then
+ if state = idle then
+ if nextwrite /= nextread then
+ nextstate <= start;
+ tick_counter <= 0;
+ tx <= '0';
+ else
+ tx <= '1';
+ end if;
+ else
+ if tick_counter = tick then
+ tick_counter <= 0;
+ else
+ tick_counter <= tick_counter + 1;
+ end if;
+ end if;
+ if tick_counter = tick then
+ if state = start then
+ nextstate <= data0;
+ tx <= data_tx(0);
+ end if;
+
+ if state = data0 then
+ nextstate <= data1;
+ tx <= data_tx(1);
+ end if;
+
+ if state = data1 then
+ nextstate <= data2;
+ tx <= data_tx(2);
+ end if;
+
+ if state = data2 then
+ nextstate <= data3;
+ tx <= data_tx(3);
+ end if;
+ if state = data3 then
+ nextstate <= data4;
+ tx <= data_tx(4);
+ end if;
+ if state = data4 then
+ nextstate <= data5;
+ tx <= data_tx(5);
+ end if;
+ if state = data5 then
+ nextstate <= data6;
+ tx <= data_tx(6);
+ end if;
+ if state = data6 then
+ nextstate <= data7;
+ tx <= data_tx(7);
+ end if;
+ if state = data7 then
+ nextstate <= stop;
+ tx <= '1';
+ end if;
+ if state = stop then
+ nextstate <= idle;
+ tx <= '1';
+ end if;
+ end if;
+
+ if reset = '1' then
+ tick_counter <= 0;
+ tx <= '1';
+ nextstate <= idle;
+ end if;
+ end if;
+
+ end process;
+
+
+end Behavioral;
+
diff --git a/doc/using/UART_srcs/tx/makefile b/doc/using/UART_srcs/tx/makefile
new file mode 100644
index 000000000..83168f2f1
--- /dev/null
+++ b/doc/using/UART_srcs/tx/makefile
@@ -0,0 +1,8 @@
+
+all:
+ ghdl -i *.vhd
+ ghdl -m tb_UART_TX_8N1
+ ghdl -r tb_UART_TX_8N1 --stop-time=200us --wave=TX.ghw
+
+view:
+ gtkwave TX.ghw
diff --git a/doc/using/UART_srcs/tx/path6054.png b/doc/using/UART_srcs/tx/path6054.png
new file mode 100644
index 000000000..d2c657243
--- /dev/null
+++ b/doc/using/UART_srcs/tx/path6054.png
Binary files differ
diff --git a/doc/using/UART_srcs/tx/tb_UART_TX_8N1.vhd b/doc/using/UART_srcs/tx/tb_UART_TX_8N1.vhd
new file mode 100644
index 000000000..a485a404a
--- /dev/null
+++ b/doc/using/UART_srcs/tx/tb_UART_TX_8N1.vhd
@@ -0,0 +1,95 @@
+-- tb_UART_TX_8N1.vhd
+----------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_UART_TX_8N1 is
+end tb_UART_TX_8N1;
+
+architecture behavior of tb_UART_TX_8N1 is
+
+ --Inputs
+ signal board_clk : std_logic := '0';
+ signal reset : std_logic := '0';
+ signal send_data : std_logic_vector (7 downto 0);
+ signal wr : std_logic := '0';
+ signal tx : std_logic;
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ component UART_8N1_TX is
+ generic(
+ clk_freq : integer;
+ baudrate : integer;
+ addr_depth : integer:=5);
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ --8bit interface
+ wdata : in std_logic_vector(7 downto 0);
+ wr : in std_logic;
+ wr_en : out std_logic;
+
+ --physical wire
+ tx : out std_logic);
+end component;
+
+ constant board_clk_period : time := 10 ns;
+ constant board_clk_freq: integer :=100E6; --100MHz
+
+begin
+
+ -- Instantiate the Unit Under Test (UUT)
+UART_TX: UART_8N1_TX
+ generic map(
+ clk_freq => board_clk_freq,
+ baudrate => 115200
+ -- addr_depth => use predefined
+ )
+ port map(
+ clk => board_clk,
+ reset => reset,
+
+ wdata => send_data,
+ wr => wr,
+ wr_en => open,
+
+ tx => tx
+ );
+
+ -- Clock process definitions
+ board_clk_process : process
+ begin
+ board_clk <= '0';
+ wait for board_clk_period/2;
+ board_clk <= '1';
+ wait for board_clk_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc : process
+ begin
+ reset <= '1';
+
+ wait for 15 us;
+ reset <='0';
+ send_data<=X"A0";
+ wait until rising_edge(board_clk);
+ wr<= '1';
+
+ wait until rising_edge(board_clk);
+ wr<= '0';
+
+ wait for 5 us;
+
+ wait until rising_edge(board_clk);
+ wr<= '1';
+ send_data<=X"B1";
+
+ wait until rising_edge(board_clk);
+ wr<= '0';
+ wait;
+ end process;
+
+ end;
diff --git a/doc/using/UART_srcs/tx/tx.gtkw b/doc/using/UART_srcs/tx/tx.gtkw
new file mode 100644
index 000000000..92e8cd730
--- /dev/null
+++ b/doc/using/UART_srcs/tx/tx.gtkw
@@ -0,0 +1,33 @@
+[*]
+[*] GTKWave Analyzer v3.3.67 (w)1999-2015 BSI
+[*] Fri Dec 16 19:12:23 2016
+[*]
+[dumpfile] "/home/red/artikel_uart/tx/TX.ghw"
+[dumpfile_mtime] "Fri Dec 16 19:08:11 2016"
+[dumpfile_size] 349946
+[savefile] "/home/red/artikel_uart/tx/tx.gtkw"
+[timestart] 0
+[size] 1920 1016
+[pos] -83 -83
+*-35.000000 106965000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] top.
+[treeopen] top.tb_uart_tx_8n1.
+[treeopen] top.tb_uart_tx_8n1.uart_tx.
+[sst_width] 218
+[signals_width] 142
+[sst_expanded] 1
+[sst_vpaned_height] 215
+@28
+top.tb_uart_tx_8n1.board_clk
+top.tb_uart_tx_8n1.reset
+[color] 5
+top.tb_uart_tx_8n1.wr
+@22
+#{top.tb_uart_tx_8n1.send_data[7:0]} top.tb_uart_tx_8n1.send_data[7] top.tb_uart_tx_8n1.send_data[6] top.tb_uart_tx_8n1.send_data[5] top.tb_uart_tx_8n1.send_data[4] top.tb_uart_tx_8n1.send_data[3] top.tb_uart_tx_8n1.send_data[2] top.tb_uart_tx_8n1.send_data[1] top.tb_uart_tx_8n1.send_data[0]
+@200
+-FIFO_Control
+@22
+#{top.tb_uart_tx_8n1.uart_tx.nextread[4:0]} top.tb_uart_tx_8n1.uart_tx.nextread[4] top.tb_uart_tx_8n1.uart_tx.nextread[3] top.tb_uart_tx_8n1.uart_tx.nextread[2] top.tb_uart_tx_8n1.uart_tx.nextread[1] top.tb_uart_tx_8n1.uart_tx.nextread[0]
+#{top.tb_uart_tx_8n1.uart_tx.nextwrite[4:0]} top.tb_uart_tx_8n1.uart_tx.nextwrite[4] top.tb_uart_tx_8n1.uart_tx.nextwrite[3] top.tb_uart_tx_8n1.uart_tx.nextwrite[2] top.tb_uart_tx_8n1.uart_tx.nextwrite[1] top.tb_uart_tx_8n1.uart_tx.nextwrite[0]
+[pattern_trace] 1
+[pattern_trace] 0
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-09 22:54:38 +0000