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-rw-r--r--doc/using/UART_srcs/capitalisation/Zeichnung.svg225
-rw-r--r--doc/using/UART_srcs/capitalisation/capitalisation.pngbin48212 -> 0 bytes
-rw-r--r--doc/using/UART_srcs/capitalisation/capitalisation.vhd51
-rw-r--r--doc/using/UART_srcs/capitalisation/makefile18
-rw-r--r--doc/using/UART_srcs/capitalisation/tb_capitalisation.vhd89
-rw-r--r--doc/using/UART_srcs/capitalisation/top_capitalisation.vhd126
-rw-r--r--doc/using/UART_srcs/capitalisation/zeichnung.pngbin15065 -> 0 bytes
7 files changed, 0 insertions, 509 deletions
diff --git a/doc/using/UART_srcs/capitalisation/Zeichnung.svg b/doc/using/UART_srcs/capitalisation/Zeichnung.svg
deleted file mode 100644
index e64d02ab5..000000000
--- a/doc/using/UART_srcs/capitalisation/Zeichnung.svg
+++ /dev/null
@@ -1,225 +0,0 @@
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diff --git a/doc/using/UART_srcs/capitalisation/capitalisation.png b/doc/using/UART_srcs/capitalisation/capitalisation.png
deleted file mode 100644
index 5b6dcbc37..000000000
--- a/doc/using/UART_srcs/capitalisation/capitalisation.png
+++ /dev/null
Binary files differ
diff --git a/doc/using/UART_srcs/capitalisation/capitalisation.vhd b/doc/using/UART_srcs/capitalisation/capitalisation.vhd
deleted file mode 100644
index e904eda95..000000000
--- a/doc/using/UART_srcs/capitalisation/capitalisation.vhd
+++ /dev/null
@@ -1,51 +0,0 @@
--- loopback engine
-----------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-entity capitalisation is
- port(
- clk : in std_logic;
- reset : in std_logic;
- --in
- rdata : in std_logic_vector(7 downto 0);
- rd_en : in std_logic;
- rd : out std_logic;
- --out
- wdata : out std_logic_vector(7 downto 0);
- wr_en : in std_logic;
- wr : out std_logic
- );
-end;
-
-architecture Behavioral of capitalisation is
-
-
-
-begin
-
-
- process(clk)
- begin
- wr<='0';
- rd<='0';
- if wr_en='1' and rd_en ='1' then
- wr<='1';
- rd<='1';
- if (unsigned(rdata)>X"60") and
- (unsigned(rdata)<X"7B") then
- wdata<=rdata(7 downto 6 )&'0'& rdata(4 downto 0);
- else
- wdata<=rdata;
- end if;
- end if;
- if reset='1' then
- wr<='0';
- end if;
- end process;
-
-
-
-end Behavioral;
-
diff --git a/doc/using/UART_srcs/capitalisation/makefile b/doc/using/UART_srcs/capitalisation/makefile
deleted file mode 100644
index ad8a01b04..000000000
--- a/doc/using/UART_srcs/capitalisation/makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-all:
- rm -rf work
- mkdir work
-
- ghdl -a --work=work --workdir=work top_capitalisation.vhd
- ghdl -a --work=work --workdir=work capitalisation.vhd
- ghdl -a --work=work --workdir=work ../rx/UART_RX_8N1.vhd
- ghdl -a --work=work --workdir=work ../tx/UART_TX_8N1.vhd
- ghdl -a --work=work --workdir=work capitalisation.vhd
-
- ghdl -a --work=work --workdir=work tb_capitalisation.vhd
- ghdl -e --workdir=work -Pwork tb_capitalisation
- ghdl -r tb_capitalisation --wave=tbench.ghw --stop-time=700us
-
-
-view:
- gtkwave tbench.ghw a.gtkw
-
diff --git a/doc/using/UART_srcs/capitalisation/tb_capitalisation.vhd b/doc/using/UART_srcs/capitalisation/tb_capitalisation.vhd
deleted file mode 100644
index 364142946..000000000
--- a/doc/using/UART_srcs/capitalisation/tb_capitalisation.vhd
+++ /dev/null
@@ -1,89 +0,0 @@
--- tb_capitalisation.vhd
-----------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity tb_capitalisation is
-end tb_capitalisation;
-
-architecture behavior of tb_capitalisation is
-
- constant board_clk_period : time := 10 ns;
- constant board_clk_freq: integer :=100E6; --100MHz
-
- signal board_clk : std_logic := '0';
- signal reset : std_logic := '0';
- signal rx : std_logic := '1';
- signal tx : std_logic;
-
- procedure tx_char (signal txpin : out std_logic;
- txdata : in character; baudrate : in integer) is
- constant bittime : time := (integer(1000000000.0/real(baudrate))) * 1 ns;
- variable c : std_logic_vector(7 downto 0);
- begin
- c := std_logic_vector(to_unsigned(character'pos(txdata), 8));
- txpin <= '0'; -- Startbit
- wait for bittime;
- for i in 0 to 7 loop
- txpin <= c(i);
- wait for bittime;
- end loop;
- txpin <= '1'; -- Stopbit
- wait for bittime;
- end tx_char;
-
- -- Component Declaration for the Unit Under Test (UUT)
-component top_capitalisation is
- generic (clk_freq : integer;
- baudrate : integer);
- port(
- board_clk : in std_logic ;
- reset : in std_logic ;
- rx : in std_logic ;
- tx : out std_logic );
-end component;
-
-begin
- -- Instantiate the Unit Under Test (UUT)
-UART_example: top_capitalisation
- generic map (
- clk_freq => board_clk_freq,
- baudrate =>115200)
- port map(
- board_clk => board_clk,
- reset => reset,
- rx => rx,
- tx => tx );
-
- process
- begin
- wait for 80000 ns;
- tx_char(RX, '$', 115200);
- tx_char(RX, 'g', 115200);
- tx_char(RX, '#', 115200);
- wait for 50 us;
- tx_char(RX, 'b', 115200);
- tx_char(RX, 'c', 115200);
- wait; -- will wait forever
- end process;
-
- -- Clock process definitions
- board_clk_process : process
- begin
- board_clk <= '0';
- wait for board_clk_period/2;
- board_clk <= '1';
- wait for board_clk_period/2;
- end process;
-
- -- Stimulus process
- process
- begin
- reset <= '1';
- wait for 100 ns;
- reset <='0';
- wait;
- end process;
-
-end;
diff --git a/doc/using/UART_srcs/capitalisation/top_capitalisation.vhd b/doc/using/UART_srcs/capitalisation/top_capitalisation.vhd
deleted file mode 100644
index 01c8e3585..000000000
--- a/doc/using/UART_srcs/capitalisation/top_capitalisation.vhd
+++ /dev/null
@@ -1,126 +0,0 @@
--- top_capitalisation.vhd
-----------------------------------------------------------------------
-
--- top_capitalisation
--- |
--- + capitalisation
--- + UART_8N1_RX
--- + UART_8N1_TX
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity top_capitalisation is
- generic (clk_freq : integer;
- baudrate : integer);
- port(
- board_clk : in std_logic ;
- reset : in std_logic ;
- rx : in std_logic ;
- tx : out std_logic );
-end top_capitalisation;
-
-architecture behavior of top_capitalisation is
- signal rd_en : std_logic;
- signal rdata : std_logic_vector (7 downto 0);
- signal rd : std_logic;
-
- signal wr_en : std_logic;
- signal wdata : std_logic_vector (7 downto 0);
- signal wr : std_logic;
-
-component capitalisation is
- port(
- clk : in std_logic;
- reset : in std_logic;
- --in
- rdata : in std_logic_vector(7 downto 0);
- rd_en : in std_logic;
- rd : out std_logic;
- --out
- wdata : out std_logic_vector(7 downto 0);
- wr_en : in std_logic;
- wr : out std_logic
- );
-end component;
-
-component UART_8N1_RX is
- generic (clk_freq : integer;
- baudrate : integer);
- port(
- clk : in std_logic;
- reset : in std_logic;
- --8bit interface
- rdata : out std_logic_vector(7 downto 0);
- rd : in std_logic;
- rd_en : out std_logic;
- --physical wire RX
- rx : in std_logic
- );
-end component;
-
-component UART_8N1_TX is
- generic(
- clk_freq : integer;
- baudrate : integer;
- addr_depth : integer:=5);
- port(
- clk : in std_logic;
- reset : in std_logic;
- --8bit interface
- wdata : in std_logic_vector(7 downto 0);
- wr : in std_logic;
- wr_en : out std_logic;
-
- --physical wire
- tx : out std_logic);
-end component;
-
-
-begin
-
-UART_RX:UART_8N1_RX
- generic map (
- clk_freq => clk_freq,
- baudrate =>115200)
- port map(
- clk => board_clk,
- reset => reset,
- rdata => rdata,
- rd => rd,
- rd_en => rd_en,
- --physical wire RX
- rx => rx
- );
-
-trans: capitalisation
- port map(
- clk => board_clk,
- reset => reset,
- --in
- rdata => rdata,
- rd_en => rd_en,
- rd => rd,
- --out
- wdata => wdata,
- wr_en => wr_en,
- wr => wr
- );
-
-UART_TX: UART_8N1_TX
- generic map(
- clk_freq => clk_freq,
- baudrate => 115200)
- port map(
- clk => board_clk,
- reset => reset,
- --8bit interface
- wdata => wdata,
- wr => wr,
- wr_en => wr_en,
-
- --physical wire TX
- tx => tx
- );
-end;
diff --git a/doc/using/UART_srcs/capitalisation/zeichnung.png b/doc/using/UART_srcs/capitalisation/zeichnung.png
deleted file mode 100644
index f51a0fbdd..000000000
--- a/doc/using/UART_srcs/capitalisation/zeichnung.png
+++ /dev/null
Binary files differ
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-06 15:22:23 +0000