3 files changed, 93 insertions, 0 deletions
diff --git a/testsuite/gna/issue2026/repro1.vhdl b/testsuite/gna/issue2026/repro1.vhdl
new file mode 100644
index 000000000..30d1dabe7
--- /dev/null
+++ b/testsuite/gna/issue2026/repro1.vhdl
@@ -0,0 +1,26 @@
+package test_pkg is
+    type bv_rec_t is record
+        bv : bit_vector;
+    end record;
+end package;
+
+use work.test_pkg.all;
+
+package test_constrained_generic_pkg is
+    generic (BV_WIDTH : positive);
+    subtype bv_subrec_t is bv_rec_t(bv(BV_WIDTH-1 downto 0));
+end package;
+
+package test_constrained_pkg is
+  new work.test_constrained_generic_pkg generic map (BV_WIDTH => 4);
+
+
+use work.test_constrained_pkg.all;
+
+entity test_tb is
+end entity;
+
+architecture tb of test_tb is
+    signal bv0 : bv_subrec_t;
+begin
+end architecture;
diff --git a/testsuite/gna/issue2026/test_tb.vhdl b/testsuite/gna/issue2026/test_tb.vhdl
new file mode 100644
index 000000000..4ab7f38a0
--- /dev/null
+++ b/testsuite/gna/issue2026/test_tb.vhdl
@@ -0,0 +1,53 @@
+package test_pkg is
+    type bv_rec_t is record
+        bv : bit_vector;
+    end record;
+end package;
+
+-------------------------------------------------------------------------------
+
+library work;
+use work.test_pkg.all;
+
+package test_constrained_generic_pkg is
+    generic (
+        BV_WIDTH : positive
+    );
+    subtype bv_subrec_t is bv_rec_t(bv(BV_WIDTH-1 downto 0));
+end package;
+
+-------------------------------------------------------------------------------
+
+package test_constrained_pkg is new work.test_constrained_generic_pkg generic map (BV_WIDTH => 4);
+
+-------------------------------------------------------------------------------
+
+library work;
+use work.test_pkg.all;
+
+entity dut is
+    port (
+        input : in bv_rec_t
+    );
+end entity;
+
+architecture rtl of dut is
+begin
+end architecture;
+
+-------------------------------------------------------------------------------
+
+library work;
+use work.test_constrained_pkg.all;
+
+entity test_tb is
+end entity;
+
+architecture tb of test_tb is
+    signal bv0 : bv_subrec_t;
+begin
+    i_dut : entity work.dut
+        port map (
+            input => bv0
+        );
+end architecture;
diff --git a/testsuite/gna/issue2026/testsuite.sh b/testsuite/gna/issue2026/testsuite.sh
new file mode 100755
index 000000000..381f16a91
--- /dev/null
+++ b/testsuite/gna/issue2026/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro1.vhdl
+clean
+
+analyze test_tb.vhdl
+elab_simulate test_tb
+
+clean
+
+echo "Test successful"