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-rw-r--r--src/simul/simul-vhdl_simul.adb19
1 files changed, 18 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index fbd649142..321c30130 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -2260,9 +2260,26 @@ package body Simul.Vhdl_Simul is
end loop;
end;
return;
+ when Type_Record =>
+ for I in Dst.Typ.Rec.E'Range loop
+ declare
+ E : Rec_El_Type renames Dst.Typ.Rec.E (I);
+ begin
+ Connect ((Dst.Sig,
+ (Dst.Offs.Net_Off + E.Offs.Net_Off,
+ Dst.Offs.Mem_Off + E.Offs.Mem_Off),
+ E.Typ),
+ (Src.Sig,
+ (Src.Offs.Net_Off + E.Offs.Net_Off,
+ Src.Offs.Mem_Off + E.Offs.Mem_Off),
+ Src.Typ.Rec.E (I).Typ),
+ Mode);
+ end;
+ end loop;
when Type_Logic
| Type_Bit
- | Type_Discrete =>
+ | Type_Discrete
+ | Type_Float =>
declare
S, D : Ghdl_Signal_Ptr;
begin