diff options
| -rw-r--r-- | src/files_map.adb | 3 | ||||
| -rw-r--r-- | src/ghdldrv/ghdlsynth.adb | 16 |
2 files changed, 13 insertions, 6 deletions
diff --git a/src/files_map.adb b/src/files_map.adb index 1d9a5c7b8..4cb6d82bf 100644 --- a/src/files_map.adb +++ b/src/files_map.adb @@ -569,6 +569,9 @@ package body Files_Map is then return Language_Verilog; end if; + if Ext (E + 1 .. Ext'Last) = "psl" then + return Language_Psl; + end if; when others => return Language_Unknown; end case; diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb index fda42bcbc..ffb3fb10d 100644 --- a/src/ghdldrv/ghdlsynth.adb +++ b/src/ghdldrv/ghdlsynth.adb @@ -310,12 +310,16 @@ package body Ghdlsynth is Libraries.Work_Library_Name := Id; Libraries.Load_Work_Library (True); else - if Files_Map.Find_Language (Arg) /= Language_Vhdl then - Errorout.Report_Msg - (Warnid_Library, Option, No_Source_Coord, - "unexpected extension for vhdl file %i", - (1 => +Name_Table.Get_Identifier (Arg))); - end if; + case Files_Map.Find_Language (Arg) is + when Language_Vhdl + | Language_Psl => + null; + when others => + Errorout.Report_Msg + (Warnid_Library, Option, No_Source_Coord, + "unexpected extension for vhdl file %i", + (1 => +Name_Table.Get_Identifier (Arg))); + end case; Ghdlcomp.Compile_Load_File (Arg); end if; |