diff options
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 4 | ||||
| -rw-r--r-- | src/synth/synth-static_oper.adb | 14 |
2 files changed, 12 insertions, 6 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index f629fd21a..67d51d552 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -612,8 +612,10 @@ package body Netlists.Disp_Vhdl is if Wd > 1 then Disp_Template (" (\n0 downto \n1)", Inst, (0 => Off + Wd - 1, 1 => Off)); - else + elsif Wd = 1 then Disp_Template (" (\n0)", Inst, (0 => Off)); + else + Disp_Template (" (-1 downto 0)", Inst); end if; end if; end Disp_Extract; diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index 02cd54d3d..be4857990 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -402,21 +402,25 @@ package body Synth.Static_Oper is declare Ret_Typ : constant Type_Acc := Get_Value_Type (Syn_Inst, Get_Return_Type (Imp)); + L_Len : constant Iir_Index32 := + Iir_Index32 (Get_Bound_Length (Left.Typ, 1)); + R_Len : constant Iir_Index32 := + Iir_Index32 (Get_Bound_Length (Right.Typ, 1)); Bnd : Bound_Type; Res_Typ : Type_Acc; Arr : Value_Array_Acc; begin Bnd := Oper.Create_Bounds_From_Length (Syn_Inst, Get_Index_Type (Get_Type (Expr), 0), - Left.Arr.Len + Right.Arr.Len); + L_Len + R_Len); Res_Typ := Create_Onedimensional_Array_Subtype (Ret_Typ, Bnd); - Arr := Create_Value_Array (Left.Arr.Len + Right.Arr.Len); - for I in Left.Arr.V'Range loop + Arr := Create_Value_Array (L_Len + R_Len); + for I in 1 .. L_Len loop Arr.V (I) := Left.Arr.V (I); end loop; - for I in Right.Arr.V'Range loop - Arr.V (Left.Arr.Len + I) := Right.Arr.V (I); + for I in 1 .. R_Len loop + Arr.V (L_Len + I) := Right.Arr.V (I); end loop; return Create_Value_Const_Array (Res_Typ, Arr); end; |