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-rw-r--r--src/ghdldrv/ghdlsimul.adb5
-rw-r--r--src/ghdldrv/ghdlsynth.adb6
-rw-r--r--src/synth/elab-vhdl_annotations.adb (renamed from src/vhdl/vhdl-annotations.adb)4
-rw-r--r--src/synth/elab-vhdl_annotations.ads (renamed from src/vhdl/vhdl-annotations.ads)4
-rw-r--r--src/synth/elab-vhdl_context.ads2
-rw-r--r--src/synth/elab-vhdl_debug.adb4
-rw-r--r--src/synth/elab-vhdl_insts.adb10
-rw-r--r--src/synth/synth-vhdl_expr.adb3
8 files changed, 20 insertions, 18 deletions
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb
index 94d7c0e97..03322c54a 100644
--- a/src/ghdldrv/ghdlsimul.adb
+++ b/src/ghdldrv/ghdlsimul.adb
@@ -31,7 +31,8 @@ with Errorout;
with Vhdl.Nodes; use Vhdl.Nodes;
with Vhdl.Std_Package;
with Vhdl.Canon;
-with Vhdl.Annotations;
+
+with Elab.Vhdl_Annotations;
with Grt.Options;
with Grt.Types;
@@ -66,7 +67,7 @@ package body Ghdlsimul is
Vhdl.Canon.Canon_Flag_Add_Labels := True;
Vhdl.Canon.Canon_Flag_Add_Suspend_State := True;
- Vhdl.Annotations.Flag_Synthesis := True;
+ Elab.Vhdl_Annotations.Flag_Synthesis := True;
-- Do not canon concurrent statements.
Vhdl.Canon.Canon_Flag_Concurrent_Stmts := False;
diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb
index 9a70bc912..711ad66bc 100644
--- a/src/ghdldrv/ghdlsynth.adb
+++ b/src/ghdldrv/ghdlsynth.adb
@@ -35,7 +35,6 @@ with Vhdl.Scanner;
with Vhdl.Std_Package;
with Vhdl.Canon;
with Vhdl.Configuration;
-with Vhdl.Annotations;
with Vhdl.Utils;
with Netlists.Dump;
@@ -46,6 +45,7 @@ with Netlists.Errors;
with Netlists.Inference;
with Netlists.Rename;
+with Elab.Vhdl_Annotations;
with Elab.Vhdl_Context; use Elab.Vhdl_Context;
with Elab.Vhdl_Insts;
with Elab.Debugger;
@@ -264,7 +264,7 @@ package body Ghdlsynth is
procedure Synth_Compile_Init (Enable_Translate_Off : Boolean;
Load_Work : Boolean) is
begin
- Vhdl.Annotations.Flag_Synthesis := True;
+ Elab.Vhdl_Annotations.Flag_Synthesis := True;
if Enable_Translate_Off then
Vhdl.Scanner.Flag_Comment_Keyword := True;
Vhdl.Scanner.Flag_Pragma_Comment := True;
@@ -522,7 +522,7 @@ package body Ghdlsynth is
pragma Assert (Is_Expr_Pool_Empty);
- Vhdl.Annotations.Finalize_Annotate;
+ Elab.Vhdl_Annotations.Finalize_Annotate;
Synth.Vhdl_Context.Free_Base_Instance;
return Res;
diff --git a/src/vhdl/vhdl-annotations.adb b/src/synth/elab-vhdl_annotations.adb
index 194341730..2993fde3f 100644
--- a/src/vhdl/vhdl-annotations.adb
+++ b/src/synth/elab-vhdl_annotations.adb
@@ -23,7 +23,7 @@ with Vhdl.Errors; use Vhdl.Errors;
with Vhdl.Utils; use Vhdl.Utils;
with Vhdl.Ieee.Std_Logic_1164;
-package body Vhdl.Annotations is
+package body Elab.Vhdl_Annotations is
procedure Annotate_Declaration_List
(Block_Info: Sim_Info_Acc; Decl_Chain: Iir);
procedure Annotate_Sequential_Statement_Chain
@@ -1532,4 +1532,4 @@ package body Vhdl.Annotations is
begin
return Info_Node.Table (Target);
end Get_Info;
-end Vhdl.Annotations;
+end Elab.Vhdl_Annotations;
diff --git a/src/vhdl/vhdl-annotations.ads b/src/synth/elab-vhdl_annotations.ads
index 34fa26e12..15f643c25 100644
--- a/src/vhdl/vhdl-annotations.ads
+++ b/src/synth/elab-vhdl_annotations.ads
@@ -17,7 +17,7 @@
with Types; use Types;
with Vhdl.Nodes; use Vhdl.Nodes;
-package Vhdl.Annotations is
+package Elab.Vhdl_Annotations is
-- If True, annotate for synthesis.
Flag_Synthesis : Boolean := False;
@@ -160,4 +160,4 @@ package Vhdl.Annotations is
-- Expand the annotation table. This is automatically done by Annotate,
-- to be used only by debugger.
procedure Annotate_Expand_Table;
-end Vhdl.Annotations;
+end Elab.Vhdl_Annotations;
diff --git a/src/synth/elab-vhdl_context.ads b/src/synth/elab-vhdl_context.ads
index e02ed714e..8598bbf56 100644
--- a/src/synth/elab-vhdl_context.ads
+++ b/src/synth/elab-vhdl_context.ads
@@ -19,9 +19,9 @@
with Types; use Types;
with Areapools;
-with Vhdl.Annotations; use Vhdl.Annotations;
with Vhdl.Nodes; use Vhdl.Nodes;
+with Elab.Vhdl_Annotations; use Elab.Vhdl_Annotations;
with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes;
with Elab.Vhdl_Values; use Elab.Vhdl_Values;
diff --git a/src/synth/elab-vhdl_debug.adb b/src/synth/elab-vhdl_debug.adb
index e4b83375b..8db0f2058 100644
--- a/src/synth/elab-vhdl_debug.adb
+++ b/src/synth/elab-vhdl_debug.adb
@@ -25,6 +25,7 @@ with Errorout;
with Elab.Debugger; use Elab.Debugger;
with Elab.Memtype; use Elab.Memtype;
+with Elab.Vhdl_Annotations;
with Elab.Vhdl_Values; use Elab.Vhdl_Values;
with Elab.Vhdl_Values.Debug; use Elab.Vhdl_Values.Debug;
@@ -38,7 +39,6 @@ with Vhdl.Parse;
with Vhdl.Sem_Scopes;
with Vhdl.Sem_Expr;
with Vhdl.Canon;
-with Vhdl.Annotations;
with Vhdl.Std_Package;
with Vhdl.Prints;
@@ -1308,7 +1308,7 @@ package body Elab.Vhdl_Debug is
Vhdl.Prints.Disp_Expression (Expr);
New_Line;
- Vhdl.Annotations.Annotate_Expand_Table;
+ Elab.Vhdl_Annotations.Annotate_Expand_Table;
Vhdl.Canon.Canon_Expression (Expr);
Mark_Expr_Pool (Marker);
diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb
index a3a1a8c38..2c98a1b73 100644
--- a/src/synth/elab-vhdl_insts.adb
+++ b/src/synth/elab-vhdl_insts.adb
@@ -22,11 +22,11 @@ with Areapools;
with Vhdl.Utils; use Vhdl.Utils;
with Vhdl.Std_Package;
-with Vhdl.Annotations;
with Vhdl.Configuration; use Vhdl.Configuration;
with Vhdl.Errors; use Vhdl.Errors;
with Elab.Memtype;
+with Elab.Vhdl_Annotations;
with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes;
with Elab.Vhdl_Values; use Elab.Vhdl_Values;
with Elab.Vhdl_Decls; use Elab.Vhdl_Decls;
@@ -863,11 +863,11 @@ package body Elab.Vhdl_Insts is
Entity := Get_Entity (Arch);
-- Annotate units.
- Vhdl.Annotations.Flag_Synthesis := True;
- Vhdl.Annotations.Initialize_Annotate;
- Vhdl.Annotations.Annotate (Vhdl.Std_Package.Std_Standard_Unit);
+ Elab.Vhdl_Annotations.Flag_Synthesis := True;
+ Elab.Vhdl_Annotations.Initialize_Annotate;
+ Elab.Vhdl_Annotations.Annotate (Vhdl.Std_Package.Std_Standard_Unit);
for I in Design_Units.First .. Design_Units.Last loop
- Vhdl.Annotations.Annotate (Design_Units.Table (I));
+ Elab.Vhdl_Annotations.Annotate (Design_Units.Table (I));
end loop;
-- Use global memory.
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb
index 5698b7987..26f1f2ef5 100644
--- a/src/synth/synth-vhdl_expr.adb
+++ b/src/synth/synth-vhdl_expr.adb
@@ -27,7 +27,6 @@ with Vhdl.Std_Package;
with Vhdl.Errors; use Vhdl.Errors;
with Vhdl.Utils; use Vhdl.Utils;
with Vhdl.Evaluation; use Vhdl.Evaluation;
-with Vhdl.Annotations; use Vhdl.Annotations;
with PSL.Nodes;
with PSL.Errors;
@@ -38,6 +37,7 @@ with Netlists.Utils; use Netlists.Utils;
with Netlists.Locations;
with Elab.Memtype; use Elab.Memtype;
+with Elab.Vhdl_Annotations;
with Elab.Vhdl_Heap; use Elab.Vhdl_Heap;
with Elab.Vhdl_Types; use Elab.Vhdl_Types;
with Elab.Vhdl_Expr;
@@ -474,6 +474,7 @@ package body Synth.Vhdl_Expr is
Atype : Node;
Dim : Dim_Type) return Bound_Type
is
+ use Elab.Vhdl_Annotations;
Info : constant Sim_Info_Acc := Get_Info (Atype);
begin
if Info = null then
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-15 10:53:43 +0000