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-rw-r--r--testsuite/synth/dff03/dff01.vhdl20
-rw-r--r--testsuite/synth/dff03/dff02.vhdl20
-rw-r--r--testsuite/synth/dff03/dff03.vhdl20
-rw-r--r--testsuite/synth/dff03/dff04.vhdl20
-rw-r--r--testsuite/synth/dff03/dff05.vhdl20
-rw-r--r--testsuite/synth/dff03/dff06.vhdl20
-rw-r--r--testsuite/synth/dff03/tb_dff01.vhdl53
-rw-r--r--testsuite/synth/dff03/tb_dff02.vhdl53
-rw-r--r--testsuite/synth/dff03/tb_dff03.vhdl63
-rw-r--r--testsuite/synth/dff03/tb_dff04.vhdl63
-rw-r--r--testsuite/synth/dff03/tb_dff05.vhdl63
-rw-r--r--testsuite/synth/dff03/tb_dff06.vhdl63
-rwxr-xr-xtestsuite/synth/dff03/testsuite.sh16
13 files changed, 494 insertions, 0 deletions
diff --git a/testsuite/synth/dff03/dff01.vhdl b/testsuite/synth/dff03/dff01.vhdl
new file mode 100644
index 000000000..6528e6091
--- /dev/null
+++ b/testsuite/synth/dff03/dff01.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff01 is
+ port (q : out std_logic;
+ d : std_logic;
+ en1 : std_logic;
+ en2 : std_logic;
+ clk : std_logic);
+end dff01;
+
+architecture behav of dff01 is
+begin
+ process (clk) is
+ begin
+ if en1 = '1' and rising_edge (clk) then
+ q <= d;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff03/dff02.vhdl b/testsuite/synth/dff03/dff02.vhdl
new file mode 100644
index 000000000..346a50c3d
--- /dev/null
+++ b/testsuite/synth/dff03/dff02.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff02 is
+ port (q : out std_logic;
+ d : std_logic;
+ en1 : std_logic;
+ en2 : std_logic;
+ clk : std_logic);
+end dff02;
+
+architecture behav of dff02 is
+begin
+ process (clk) is
+ begin
+ if rising_edge (clk) and en1 = '1' then
+ q <= d;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff03/dff03.vhdl b/testsuite/synth/dff03/dff03.vhdl
new file mode 100644
index 000000000..0d2291c3a
--- /dev/null
+++ b/testsuite/synth/dff03/dff03.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff03 is
+ port (q : out std_logic;
+ d : std_logic;
+ en1 : std_logic;
+ en2 : std_logic;
+ clk : std_logic);
+end dff03;
+
+architecture behav of dff03 is
+begin
+ process (clk) is
+ begin
+ if (rising_edge (clk) and en1 = '1') and en2 = '1' then
+ q <= d;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff03/dff04.vhdl b/testsuite/synth/dff03/dff04.vhdl
new file mode 100644
index 000000000..58d1f9b32
--- /dev/null
+++ b/testsuite/synth/dff03/dff04.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff04 is
+ port (q : out std_logic;
+ d : std_logic;
+ en1 : std_logic;
+ en2 : std_logic;
+ clk : std_logic);
+end dff04;
+
+architecture behav of dff04 is
+begin
+ process (clk) is
+ begin
+ if en2 = '1' and (rising_edge (clk) and en1 = '1') then
+ q <= d;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff03/dff05.vhdl b/testsuite/synth/dff03/dff05.vhdl
new file mode 100644
index 000000000..e1d147e5d
--- /dev/null
+++ b/testsuite/synth/dff03/dff05.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff05 is
+ port (q : out std_logic;
+ d : std_logic;
+ en1 : std_logic;
+ en2 : std_logic;
+ clk : std_logic);
+end dff05;
+
+architecture behav of dff05 is
+begin
+ process (clk) is
+ begin
+ if en2 = '1' and (en1 = '1' and rising_edge (clk)) then
+ q <= d;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff03/dff06.vhdl b/testsuite/synth/dff03/dff06.vhdl
new file mode 100644
index 000000000..cf6d08a67
--- /dev/null
+++ b/testsuite/synth/dff03/dff06.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff06 is
+ port (q : out std_logic;
+ d : std_logic;
+ en1 : std_logic;
+ en2 : std_logic;
+ clk : std_logic);
+end dff06;
+
+architecture behav of dff06 is
+begin
+ process (clk) is
+ begin
+ if (en2 = '1' and en1 = '1') and rising_edge (clk) then
+ q <= d;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff03/tb_dff01.vhdl b/testsuite/synth/dff03/tb_dff01.vhdl
new file mode 100644
index 000000000..85d95f47b
--- /dev/null
+++ b/testsuite/synth/dff03/tb_dff01.vhdl
@@ -0,0 +1,53 @@
+entity tb_dff01 is
+end tb_dff01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff01 is
+ signal clk : std_logic;
+ signal en1 : std_logic;
+ signal en2 : std_logic;
+ signal din : std_logic;
+ signal dout : std_logic;
+begin
+ dut: entity work.dff01
+ port map (
+ q => dout,
+ d => din,
+ en1 => en1,
+ en2 => en2,
+ clk => clk);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ en1 <= '1';
+ en2 <= '1';
+ din <= '0';
+ pulse;
+ assert dout = '0' severity failure;
+
+ din <= '1';
+ pulse;
+ assert dout = '1' severity failure;
+
+ en1 <= '0';
+ din <= '0';
+ pulse;
+ assert dout = '1' severity failure;
+
+ en1 <= '1';
+ din <= '0';
+ pulse;
+ assert dout = '0' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff03/tb_dff02.vhdl b/testsuite/synth/dff03/tb_dff02.vhdl
new file mode 100644
index 000000000..5c93403de
--- /dev/null
+++ b/testsuite/synth/dff03/tb_dff02.vhdl
@@ -0,0 +1,53 @@
+entity tb_dff02 is
+end tb_dff02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff02 is
+ signal clk : std_logic;
+ signal en1 : std_logic;
+ signal en2 : std_logic;
+ signal din : std_logic;
+ signal dout : std_logic;
+begin
+ dut: entity work.dff02
+ port map (
+ q => dout,
+ d => din,
+ en1 => en1,
+ en2 => en2,
+ clk => clk);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ en1 <= '1';
+ en2 <= '1';
+ din <= '0';
+ pulse;
+ assert dout = '0' severity failure;
+
+ din <= '1';
+ pulse;
+ assert dout = '1' severity failure;
+
+ en1 <= '0';
+ din <= '0';
+ pulse;
+ assert dout = '1' severity failure;
+
+ en1 <= '1';
+ din <= '0';
+ pulse;
+ assert dout = '0' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff03/tb_dff03.vhdl b/testsuite/synth/dff03/tb_dff03.vhdl
new file mode 100644
index 000000000..f70abda07
--- /dev/null
+++ b/testsuite/synth/dff03/tb_dff03.vhdl
@@ -0,0 +1,63 @@
+entity tb_dff03 is
+end tb_dff03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff03 is
+ signal clk : std_logic;
+ signal en1 : std_logic;
+ signal en2 : std_logic;
+ signal din : std_logic;
+ signal dout : std_logic;
+begin
+ dut: entity work.dff03
+ port map (
+ q => dout,
+ d => din,
+ en1 => en1,
+ en2 => en2,
+ clk => clk);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ en1 <= '1';
+ en2 <= '1';
+ din <= '0';
+ pulse;
+ assert dout = '0' severity failure;
+
+ din <= '1';
+ pulse;
+ assert dout = '1' severity failure;
+
+ en1 <= '0';
+ din <= '0';
+ pulse;
+ assert dout = '1' severity failure;
+
+ en1 <= '1';
+ din <= '0';
+ pulse;
+ assert dout = '0' severity failure;
+
+ en2 <= '0';
+ din <= '1';
+ pulse;
+ assert dout = '0' severity failure;
+
+ en2 <= '1';
+ din <= '1';
+ pulse;
+ assert dout = '1' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff03/tb_dff04.vhdl b/testsuite/synth/dff03/tb_dff04.vhdl
new file mode 100644
index 000000000..0330c99bb
--- /dev/null
+++ b/testsuite/synth/dff03/tb_dff04.vhdl
@@ -0,0 +1,63 @@
+entity tb_dff04 is
+end tb_dff04;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff04 is
+ signal clk : std_logic;
+ signal en1 : std_logic;
+ signal en2 : std_logic;
+ signal din : std_logic;
+ signal dout : std_logic;
+begin
+ dut: entity work.dff04
+ port map (
+ q => dout,
+ d => din,
+ en1 => en1,
+ en2 => en2,
+ clk => clk);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ en1 <= '1';
+ en2 <= '1';
+ din <= '0';
+ pulse;
+ assert dout = '0' severity failure;
+
+ din <= '1';
+ pulse;
+ assert dout = '1' severity failure;
+
+ en1 <= '0';
+ din <= '0';
+ pulse;
+ assert dout = '1' severity failure;
+
+ en1 <= '1';
+ din <= '0';
+ pulse;
+ assert dout = '0' severity failure;
+
+ en2 <= '0';
+ din <= '1';
+ pulse;
+ assert dout = '0' severity failure;
+
+ en2 <= '1';
+ din <= '1';
+ pulse;
+ assert dout = '1' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff03/tb_dff05.vhdl b/testsuite/synth/dff03/tb_dff05.vhdl
new file mode 100644
index 000000000..14467f3ed
--- /dev/null
+++ b/testsuite/synth/dff03/tb_dff05.vhdl
@@ -0,0 +1,63 @@
+entity tb_dff05 is
+end tb_dff05;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff05 is
+ signal clk : std_logic;
+ signal en1 : std_logic;
+ signal en2 : std_logic;
+ signal din : std_logic;
+ signal dout : std_logic;
+begin
+ dut: entity work.dff05
+ port map (
+ q => dout,
+ d => din,
+ en1 => en1,
+ en2 => en2,
+ clk => clk);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ en1 <= '1';
+ en2 <= '1';
+ din <= '0';
+ pulse;
+ assert dout = '0' severity failure;
+
+ din <= '1';
+ pulse;
+ assert dout = '1' severity failure;
+
+ en1 <= '0';
+ din <= '0';
+ pulse;
+ assert dout = '1' severity failure;
+
+ en1 <= '1';
+ din <= '0';
+ pulse;
+ assert dout = '0' severity failure;
+
+ en2 <= '0';
+ din <= '1';
+ pulse;
+ assert dout = '0' severity failure;
+
+ en2 <= '1';
+ din <= '1';
+ pulse;
+ assert dout = '1' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff03/tb_dff06.vhdl b/testsuite/synth/dff03/tb_dff06.vhdl
new file mode 100644
index 000000000..2297a723f
--- /dev/null
+++ b/testsuite/synth/dff03/tb_dff06.vhdl
@@ -0,0 +1,63 @@
+entity tb_dff06 is
+end tb_dff06;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff06 is
+ signal clk : std_logic;
+ signal en1 : std_logic;
+ signal en2 : std_logic;
+ signal din : std_logic;
+ signal dout : std_logic;
+begin
+ dut: entity work.dff06
+ port map (
+ q => dout,
+ d => din,
+ en1 => en1,
+ en2 => en2,
+ clk => clk);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ en1 <= '1';
+ en2 <= '1';
+ din <= '0';
+ pulse;
+ assert dout = '0' severity failure;
+
+ din <= '1';
+ pulse;
+ assert dout = '1' severity failure;
+
+ en1 <= '0';
+ din <= '0';
+ pulse;
+ assert dout = '1' severity failure;
+
+ en1 <= '1';
+ din <= '0';
+ pulse;
+ assert dout = '0' severity failure;
+
+ en2 <= '0';
+ din <= '1';
+ pulse;
+ assert dout = '0' severity failure;
+
+ en2 <= '1';
+ din <= '1';
+ pulse;
+ assert dout = '1' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/dff03/testsuite.sh b/testsuite/synth/dff03/testsuite.sh
new file mode 100755
index 000000000..f0c94f7f9
--- /dev/null
+++ b/testsuite/synth/dff03/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in dff01 dff02 dff03 dff04 dff05 dff06; do
+ analyze $t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t
+ clean
+
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t
+ clean
+done
+
+echo "Test successful"
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-31 01:50:31 +0000