diff options
| -rw-r--r-- | src/synth/netlists-inference.adb | 4 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_context.adb | 23 |
2 files changed, 21 insertions, 6 deletions
diff --git a/src/synth/netlists-inference.adb b/src/synth/netlists-inference.adb index 747731a11..4504a462a 100644 --- a/src/synth/netlists-inference.adb +++ b/src/synth/netlists-inference.adb @@ -394,7 +394,9 @@ package body Netlists.Inference is end if; if Els_Net = No_Net then - if Init /= No_Net then + if Init /= No_Net + and then Get_Id (Get_Net_Parent (Init)) /= Id_Const_X + then Res := Build_Idff (Ctxt, Clk, D => Ndata, Init => Init); else Res := Build_Dff (Ctxt, Clk, D => Ndata); diff --git a/src/synth/synth-vhdl_context.adb b/src/synth/synth-vhdl_context.adb index 5326c4356..81143bea9 100644 --- a/src/synth/synth-vhdl_context.adb +++ b/src/synth/synth-vhdl_context.adb @@ -265,12 +265,25 @@ package body Synth.Vhdl_Context is -- 32 bit result. if not Has_Zx then Res := Build_Const_UB32 (Ctxt, Vec (0).Val, W); - elsif Vec (0).Val = 0 and then Sext (Vec (0).Zx, Natural (W)) = not 0 - then - Res := Build_Const_Z (Ctxt, W); - else - Res := Build_Const_UL32 (Ctxt, Vec (0).Val, Vec (0).Zx, W); + return; + end if; + + if Sext (Vec (0).Zx, Natural (W)) = not 0 then + -- All bits are either Z or X. + if Vec (0).Val = 0 then + -- All bits are Z. + Res := Build_Const_Z (Ctxt, W); + return; + end if; + if Sext (Vec (0).Val, Natural (W)) = not 0 then + -- All bits are X. + Res := Build_Const_X (Ctxt, W); + return; + end if; + -- Mix of Z and X. end if; + -- Generic. + Res := Build_Const_UL32 (Ctxt, Vec (0).Val, Vec (0).Zx, W); return; else Is_Full (Vec, W, Is_0, Is_X, Is_Z); |