diff options
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 3 | ||||
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index b131d5462..b400a8106 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -614,7 +614,8 @@ package body Simul.Vhdl_Elab is if Get_Collapse_Signal_Flag (Assoc) and then Formal_Ep.Offs.Mem_Off = 0 and then Actual_Ep.Offs.Mem_Off = 0 - and then Actual_Base.Typ.W = Formal_Base.Typ.W + and then Actual_Base.Typ.W = Actual_Ep.Typ.W + and then Formal_Base.Typ.W = Formal_Ep.Typ.W then -- Full collapse. pragma Assert (Signals_Table.Table (Formal_Sig).Collapsed_By diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 2f3c2ef87..ebfdc17c8 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2216,7 +2216,7 @@ package body Simul.Vhdl_Simul is Create_Signal (Val + Size_Type (I - 1) * Typ.Arr_El.Sz, Sig_Off + (Len - I) * Typ.Arr_El.W, El_Type, Typ.Arr_El, - Vec, Already_Resolved); + Vec, Sub_Resolved); end loop; end; when Type_Record => |