diff options
| -rw-r--r-- | doc/ghdl.texi | 2 | ||||
| -rw-r--r-- | libraries/vendors/compile-uvvm.ps1 | 1 | ||||
| -rw-r--r-- | libraries/vendors/compile-uvvm.sh | 1 | ||||
| -rw-r--r-- | src/ortho/debug/ortho_debug-disp.adb | 5 | ||||
| -rw-r--r-- | src/vhdl/canon.adb | 5 | ||||
| -rw-r--r-- | src/vhdl/parse.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/parse_psl.adb | 55 | ||||
| -rw-r--r-- | src/vhdl/parse_psl.ads | 2 | ||||
| -rw-r--r-- | src/vhdl/translate/trans-chap9.adb | 9 | ||||
| -rw-r--r-- | testsuite/gna/issue663/ent.vhdl | 42 | ||||
| -rw-r--r-- | testsuite/gna/issue663/repro.vhdl | 35 | ||||
| -rwxr-xr-x | testsuite/gna/issue663/testsuite.sh | 13 | ||||
| -rw-r--r-- | testsuite/gna/issue666/tb.vhdl | 21 | ||||
| -rw-r--r-- | testsuite/gna/issue666/tb2.vhdl | 21 | ||||
| -rwxr-xr-x | testsuite/gna/issue666/testsuite.sh | 10 | ||||
| -rw-r--r-- | testsuite/gna/issue679/repro.vhdl | 14 | ||||
| -rwxr-xr-x | testsuite/gna/issue679/testsuite.sh | 9 |
17 files changed, 232 insertions, 15 deletions
diff --git a/doc/ghdl.texi b/doc/ghdl.texi index cfa8ef218..ed74f57d9 100644 --- a/doc/ghdl.texi +++ b/doc/ghdl.texi @@ -976,7 +976,7 @@ As a result, @ref{2b,,-r} is just a passthrough to the binary generated in the @ @example -entity hello_world is +entity heartbeat is port ( clk: out std_logic; ) end hearbeat; diff --git a/libraries/vendors/compile-uvvm.ps1 b/libraries/vendors/compile-uvvm.ps1 index be9ca1d97..d4b7844a4 100644 --- a/libraries/vendors/compile-uvvm.ps1 +++ b/libraries/vendors/compile-uvvm.ps1 @@ -165,6 +165,7 @@ $UVVM_Util_Files = @( "uvvm_util\src\adaptations_pkg.vhd", "uvvm_util\src\string_methods_pkg.vhd", "uvvm_util\src\protected_types_pkg.vhd", + "uvvm_util\src\global_signals_and_shared_variables_pkg.vhd", "uvvm_util\src\hierarchy_linked_list_pkg.vhd", "uvvm_util\src\alert_hierarchy_pkg.vhd", "uvvm_util\src\license_pkg.vhd", diff --git a/libraries/vendors/compile-uvvm.sh b/libraries/vendors/compile-uvvm.sh index 06a3c80d3..e4c334c7a 100644 --- a/libraries/vendors/compile-uvvm.sh +++ b/libraries/vendors/compile-uvvm.sh @@ -268,6 +268,7 @@ if [ "$COMPILE_UVVM_UTILITIES" == "TRUE" ]; then uvvm_util/src/adaptations_pkg.vhd uvvm_util/src/string_methods_pkg.vhd uvvm_util/src/protected_types_pkg.vhd + uvvm_util/src/global_signals_and_shared_variables_pkg.vhd uvvm_util/src/hierarchy_linked_list_pkg.vhd uvvm_util/src/alert_hierarchy_pkg.vhd uvvm_util/src/license_pkg.vhd diff --git a/src/ortho/debug/ortho_debug-disp.adb b/src/ortho/debug/ortho_debug-disp.adb index a45bceca9..e2e5793f9 100644 --- a/src/ortho/debug/ortho_debug-disp.adb +++ b/src/ortho/debug/ortho_debug-disp.adb @@ -1108,7 +1108,10 @@ package body Ortho_Debug.Disp is Disp_Loop_Name (Stmt); Put_Line (":"); Add_Tab; - Disp_Snode (Stmt.Next, Stmt.Loop_Last); + if Stmt.Loop_Last /= Stmt then + -- Only if the loop is not empty. + Disp_Snode (Stmt.Next, Stmt.Loop_Last); + end if; Stmt := Stmt.Loop_Last; Rem_Tab; Put_Keyword ("end"); diff --git a/src/vhdl/canon.adb b/src/vhdl/canon.adb index 5d7755faf..bf6e7562a 100644 --- a/src/vhdl/canon.adb +++ b/src/vhdl/canon.adb @@ -258,8 +258,9 @@ package body Canon is end; when Iir_Kind_Object_Alias_Declaration => - Canon_Extract_Sensitivity - (Get_Name (Expr), Sensitivity_List, Is_Target); + if not Is_Target and then Is_Signal_Object (Expr) then + Add_Element (Sensitivity_List, Expr); + end if; when Iir_Kind_Constant_Declaration | Iir_Kind_Interface_Constant_Declaration diff --git a/src/vhdl/parse.adb b/src/vhdl/parse.adb index dc2d24bcd..b9e46f0fd 100644 --- a/src/vhdl/parse.adb +++ b/src/vhdl/parse.adb @@ -8109,7 +8109,7 @@ package body Parse is -- Skip 'cover' Scan; - Set_Psl_Sequence (Res, Parse_Psl.Parse_Psl_Sequence); + Set_Psl_Sequence (Res, Parse_Psl.Parse_Psl_Sequence (True)); -- No more PSL tokens after the property. Scanner.Flag_Psl := False; diff --git a/src/vhdl/parse_psl.adb b/src/vhdl/parse_psl.adb index 6a0e906e4..9b66b444e 100644 --- a/src/vhdl/parse_psl.adb +++ b/src/vhdl/parse_psl.adb @@ -92,9 +92,46 @@ package body Parse_Psl is function Parse_Parenthesis_Boolean return Node; function Parse_Boolean (Parent_Prio : Priority) return Node; - function Parse_Unary_Boolean return Node is + function Parse_Unary_Boolean (Full_Hdl_Expr : Boolean) return Node + is + use Parse; + use Iirs; + Left, Expr : Iir; + Op : Iir_Kind; begin - return Vhdl_To_Psl (Parse.Parse_Expression); + if Full_Hdl_Expr then + Expr := Parse_Expression; + else + -- Boolean operators must be parse, *except* and/or that could be at + -- upper layers (FL). + Expr := Parse_Expression (Prio_Relation); + loop + case Current_Token is + when Tok_Xor => + Op := Iir_Kind_Xor_Operator; + when Tok_Nand => + Op := Iir_Kind_Nand_Operator; + when Tok_Nor => + Op := Iir_Kind_Nor_Operator; + when Tok_Xnor => + Op := Iir_Kind_Xnor_Operator; + when others => + exit; + end case; + + Left := Expr; + Expr := Create_Iir (Op); + Set_Location (Expr, Get_Token_Location); + Set_Left (Expr, Left); + + -- Skip operator. + Scan; + + Set_Right (Expr, Parse_Expression (Prio_Relation)); + end loop; + end if; + + return Vhdl_To_Psl (Expr); end Parse_Unary_Boolean; function Parse_Boolean_Rhs (Parent_Prio : Priority; Left : Node) return Node @@ -131,7 +168,7 @@ package body Parse_Psl is function Parse_Boolean (Parent_Prio : Priority) return Node is begin - return Parse_Boolean_Rhs (Parent_Prio, Parse_Unary_Boolean); + return Parse_Boolean_Rhs (Parent_Prio, Parse_Unary_Boolean (False)); end Parse_Boolean; function Parse_Psl_Boolean return PSL_Node is @@ -162,7 +199,7 @@ package body Parse_Psl is Kind : Nkind; Op_Prio : Priority; begin - Left := Parse_Psl_Sequence; -- FIXME: allow boolean; + Left := Parse_Psl_Sequence (True); loop case Current_Token is when Tok_Semi_Colon => @@ -283,7 +320,7 @@ package body Parse_Psl is end if; end Parse_Bracket_Number; - function Parse_Psl_Sequence return Node is + function Parse_Psl_Sequence (Full_Hdl_Expr : Boolean) return Node is Res, N : Node; begin case Current_Token is @@ -314,7 +351,7 @@ package body Parse_Psl is return Res; when others => -- Repeated_SERE - Res := Parse_Unary_Boolean; + Res := Parse_Unary_Boolean (Full_Hdl_Expr); end case; loop case Current_Token is @@ -458,7 +495,7 @@ package body Parse_Psl is when Tok_Left_Paren => return Parse_Parenthesis_FL_Property; when Tok_Left_Curly => - Res := Parse_Psl_Sequence; + Res := Parse_Psl_Sequence (True); if Get_Kind (Res) = N_Braced_SERE and then Current_Token = Tok_Left_Paren then @@ -470,7 +507,7 @@ package body Parse_Psl is Res := Tmp; end if; when others => - Res := Parse_Psl_Sequence; + Res := Parse_Psl_Sequence (False); end case; return Res; end Parse_FL_Property_1; @@ -692,7 +729,7 @@ package body Parse_Psl is Set_Property (Res, Parse_Psl_Property); when N_Sequence_Declaration | N_Endpoint_Declaration => - Set_Sequence (Res, Parse_Psl_Sequence); + Set_Sequence (Res, Parse_Psl_Sequence (True)); when others => raise Internal_Error; end case; diff --git a/src/vhdl/parse_psl.ads b/src/vhdl/parse_psl.ads index 17989d8b3..1df993e82 100644 --- a/src/vhdl/parse_psl.ads +++ b/src/vhdl/parse_psl.ads @@ -20,7 +20,7 @@ with Types; use Types; with Tokens; use Tokens; package Parse_Psl is - function Parse_Psl_Sequence return PSL_Node; + function Parse_Psl_Sequence (Full_Hdl_Expr : Boolean) return PSL_Node; function Parse_Psl_Property return PSL_Node; function Parse_Psl_Boolean return PSL_Node; function Parse_Psl_Declaration (Tok : Token_Type) return PSL_Node; diff --git a/src/vhdl/translate/trans-chap9.adb b/src/vhdl/translate/trans-chap9.adb index 00295f738..3213e50a0 100644 --- a/src/vhdl/translate/trans-chap9.adb +++ b/src/vhdl/translate/trans-chap9.adb @@ -1257,6 +1257,15 @@ package body Trans.Chap9 is Fields : constant Fields_Array := Get_Fields (Kind); F : Fields_Enum; begin + case Kind is + when Iir_Kind_Object_Alias_Declaration => + -- No types to free, don't try to recurse as the name can be + -- a slice (which will then be freed). + return; + when others => + null; + end case; + for I in Fields'Range loop F := Fields (I); case F is diff --git a/testsuite/gna/issue663/ent.vhdl b/testsuite/gna/issue663/ent.vhdl new file mode 100644 index 000000000..81254d5b4 --- /dev/null +++ b/testsuite/gna/issue663/ent.vhdl @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is +end entity ent; + +architecture a of ent is + signal clk : std_logic := '0'; + + signal check_stable_in_1 : std_logic_vector(1 to 5) := "00000"; + alias check_stable_start_event_1 : std_logic is check_stable_in_1(1); + alias check_stable_end_event_1 : std_logic is check_stable_in_1(2); + alias check_stable_expr_1 : std_logic_vector(2 downto 0) is check_stable_in_1(3 to 5); + + signal check_stable_en_1 : std_logic; + + signal en, start_event, end_event, expr : std_logic := '1'; + + procedure check_stable( + signal clock : in std_logic; + signal en : in std_logic; + signal start_event : in std_logic; + signal end_event : in std_logic; + signal expr : in std_logic_vector) is + begin + wait until (falling_edge(clock) or rising_edge(clock)) and (to_x01(en) = '1'); + end; + +begin + clock : process is + begin + clk <= '1', '0' after 5 ns; + wait; + end process clock; + + check_stable_1 : check_stable(clk, + check_stable_en_1, + check_stable_start_event_1, + check_stable_end_event_1, + check_stable_expr_1); + +end architecture; diff --git a/testsuite/gna/issue663/repro.vhdl b/testsuite/gna/issue663/repro.vhdl new file mode 100644 index 000000000..220c4820f --- /dev/null +++ b/testsuite/gna/issue663/repro.vhdl @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro is +end entity repro; + +architecture a of repro is + signal clk : std_logic := '0'; + + signal check_stable_in_1 : std_logic_vector(1 to 5) := "00000"; + alias check_stable_expr_1 : std_logic_vector(2 downto 0) is check_stable_in_1(3 to 5); + + procedure check_stable( + signal clock : in std_logic; + signal expr : in std_logic_vector) is + begin + wait until rising_edge(clock); + end; + +begin + clock : process is + begin + clk <= '1', '0' after 5 ns; + wait; + end process clock; + +-- process +-- begin +-- check_stable(clk, check_stable_expr_1); +-- wait on clk, check_stable_expr_1; +-- assert check_stable_expr_1 = "000"; +-- end process; + check_stable_1 : check_stable(clk, check_stable_expr_1); + +end architecture; diff --git a/testsuite/gna/issue663/testsuite.sh b/testsuite/gna/issue663/testsuite.sh new file mode 100755 index 000000000..e25f60643 --- /dev/null +++ b/testsuite/gna/issue663/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze ent.vhdl +elab_simulate ent + +analyze repro.vhdl +elab_simulate repro + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue666/tb.vhdl b/testsuite/gna/issue666/tb.vhdl new file mode 100644 index 000000000..cb3b338de --- /dev/null +++ b/testsuite/gna/issue666/tb.vhdl @@ -0,0 +1,21 @@ +entity tb is +end entity; +architecture bench of tb is + constant kill_size : positive := 50331648; + signal s : string(1 to kill_size); + + function fun return string is + variable v : string(1 to kill_size); + begin + return "hello"; + end; +begin + proc: process + -- Segmentation fault occurs for variable too, but much faster +-- variable s : string(1 to kill_size); + begin +-- s := fun; + s <= fun; + report "pass" severity failure; + end process; +end bench; diff --git a/testsuite/gna/issue666/tb2.vhdl b/testsuite/gna/issue666/tb2.vhdl new file mode 100644 index 000000000..c7c5a35f8 --- /dev/null +++ b/testsuite/gna/issue666/tb2.vhdl @@ -0,0 +1,21 @@ +entity tb2 is +end entity; +architecture bench of tb2 is + constant kill_size : positive := 50331648; +-- signal s : string(1 to kill_size); + + function fun return string is + variable v : string(1 to kill_size); + begin + return "hello"; + end; +begin + proc: process + -- Segmentation fault occurs for variable too, but much faster + variable s : string(1 to kill_size); + begin + s := fun; +-- s <= fun; + report "pass" severity failure; + end process; +end bench; diff --git a/testsuite/gna/issue666/testsuite.sh b/testsuite/gna/issue666/testsuite.sh new file mode 100755 index 000000000..7a6bed293 --- /dev/null +++ b/testsuite/gna/issue666/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze tb.vhdl +analyze tb2.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue679/repro.vhdl b/testsuite/gna/issue679/repro.vhdl new file mode 100644 index 000000000..2aa5e63df --- /dev/null +++ b/testsuite/gna/issue679/repro.vhdl @@ -0,0 +1,14 @@ +entity repro is +end repro; + +architecture behav of repro is + signal clk : bit; + signal cyc: bit; + signal wen : bit; + signal lw : bit; +begin + -- psl default clock is clk; + + -- psl c1: assert always lw -> cyc and (next not(wen)) + -- report "error"; +end; diff --git a/testsuite/gna/issue679/testsuite.sh b/testsuite/gna/issue679/testsuite.sh new file mode 100755 index 000000000..d44aa19d3 --- /dev/null +++ b/testsuite/gna/issue679/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze -fpsl repro.vhdl + +clean + +echo "Test successful" |