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-rw-r--r--src/simul/simul-vhdl_elab.adb2
-rw-r--r--src/simul/simul-vhdl_simul.adb50
-rw-r--r--src/synth/elab-vhdl_expr.adb4
-rw-r--r--src/synth/synth-vhdl_expr.adb53
-rw-r--r--src/synth/synth-vhdl_expr.ads1
-rw-r--r--src/synth/synth-vhdl_stmts.adb2
6 files changed, 72 insertions, 40 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 8e2db63ad..49b24b42b 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -104,7 +104,7 @@ package body Simul.Vhdl_Elab is
end if;
for I in 1 .. Len loop
Mark_Resolved_Signals
- (Sig_Off + (Len - I) * Typ.Arr_El.W,
+ (Sig_Off + (I - 1) * Typ.Arr_El.W,
El_Type, Typ.Arr_El,
Vec, Already_Resolved);
end loop;
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index 4e4061fef..bbc6ab764 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -276,7 +276,7 @@ package body Simul.Vhdl_Simul is
Smem := Val.Mem + Size_Type (I - 1) * El.Sz;
end if;
Assign_Value_To_Signal
- ((El, Sig_Index (Target.Mem, (Len - I) * El.W)),
+ ((El, Sig_Index (Target.Mem, (I - 1) * El.W)),
Is_Start, Rej, After, (Val.Typ.Arr_El, Smem));
end loop;
end;
@@ -349,7 +349,7 @@ package body Simul.Vhdl_Simul is
Smem := Val.Mem + Size_Type (I - 1) * El.Sz;
end if;
Force_Signal_Value
- ((El, Sig_Index (Target.Mem, (Len - I) * El.W)),
+ ((El, Sig_Index (Target.Mem, (I - 1) * El.W)),
Kind, Mode, (Val.Typ.Arr_El, Smem));
end loop;
end;
@@ -390,7 +390,7 @@ package body Simul.Vhdl_Simul is
begin
for I in 1 .. Len loop
Add_Source (Typ.Arr_El,
- Sig_Index (Sig, (Len - I) * Typ.Arr_El.W),
+ Sig_Index (Sig, (I - 1) * Typ.Arr_El.W),
Val + Size_Type (I - 1) * Typ.Arr_El.Sz);
end loop;
end;
@@ -483,7 +483,7 @@ package body Simul.Vhdl_Simul is
Sub : Memory_Ptr;
begin
for I in 1 .. Len loop
- Sub := Sig_Index (Sig.Mem, (Len - I) * Sig.Typ.Arr_El.W);
+ Sub := Sig_Index (Sig.Mem, (I - 1) * Sig.Typ.Arr_El.W);
if Read_Signal_Flag ((Sig.Typ.Arr_El, Sub), Kind) then
return True;
end if;
@@ -768,7 +768,7 @@ package body Simul.Vhdl_Simul is
begin
for I in 1 .. Len loop
Add_Wait_Sensitivity
- (Typ.Arr_El, Sig_Index (Sig, (Len - I) * Typ.Arr_El.W));
+ (Typ.Arr_El, Sig_Index (Sig, (I - 1) * Typ.Arr_El.W));
end loop;
end;
when Type_Record =>
@@ -1175,7 +1175,7 @@ package body Simul.Vhdl_Simul is
begin
for I in 1 .. Len loop
Disconnect_Signal
- ((El, Sig_Index (Sig.Mem, (Len - I) * El.W)));
+ ((El, Sig_Index (Sig.Mem, (I - 1) * El.W)));
end loop;
end;
when Type_Record =>
@@ -1933,7 +1933,7 @@ package body Simul.Vhdl_Simul is
begin
for I in 1 .. Len loop
Add_Sensitivity
- (Typ.Arr_El, Sig_Index (Sig, (Len - I) * Typ.Arr_El.W));
+ (Typ.Arr_El, Sig_Index (Sig, (I - 1) * Typ.Arr_El.W));
end loop;
end;
when Type_Record =>
@@ -2377,7 +2377,7 @@ package body Simul.Vhdl_Simul is
for I in 1 .. Len loop
Resolver_Read_Value
((Typ.Arr_El, Dst.Mem + Size_Type (I - 1) * Typ.Arr_El.Sz),
- Sig_Index (Sig, (Len - I) * Typ.Arr_El.W),
+ Sig_Index (Sig, (I - 1) * Typ.Arr_El.W),
Mode, Index);
end loop;
end;
@@ -2427,7 +2427,7 @@ package body Simul.Vhdl_Simul is
begin
Res := Std_Time'First;
for I in 1 .. Len loop
- Sigel := Sig_Index (Sig, (Len - I) * Typ.Arr_El.W);
+ Sigel := Sig_Index (Sig, (I - 1) * Typ.Arr_El.W);
T := Exec_Read_Signal_Last (Sigel, Typ.Arr_El, Attr);
Res := Std_Time'Max (Res, T);
end loop;
@@ -2544,7 +2544,7 @@ package body Simul.Vhdl_Simul is
begin
for I in 1 .. Len loop
Exec_Read_Signal
- (Sig_Index (Sig, (Len - I) * Typ.Arr_El.W),
+ (Sig_Index (Sig, (I - 1) * Typ.Arr_El.W),
(Typ.Arr_El, Val.Mem + Size_Type (I - 1) * Typ.Arr_El.Sz),
Attr, T);
end loop;
@@ -2671,7 +2671,7 @@ package body Simul.Vhdl_Simul is
begin
for I in 1 .. Len loop
Exec_Write_Signal
- (Sig_Index (Sig, (Len - I) * Typ.Arr_El.W),
+ (Sig_Index (Sig, (I - 1) * Typ.Arr_El.W),
(Typ.Arr_El, Val.Mem + Size_Type (I - 1) * Typ.Arr_El.Sz),
Attr);
end loop;
@@ -2885,7 +2885,7 @@ package body Simul.Vhdl_Simul is
end if;
for I in 1 .. Len loop
Create_Signal (Val + Size_Type (I - 1) * Typ.Arr_El.Sz,
- Sig_Off + (Len - I) * Typ.Arr_El.W,
+ Sig_Off + (I - 1) * Typ.Arr_El.W,
El_Type, Typ.Arr_El,
Vec, Sub_Resolved);
end loop;
@@ -3051,9 +3051,9 @@ package body Simul.Vhdl_Simul is
begin
for I in 1 .. Len loop
Create_Delayed_Signal
- (Sig_Index (Sig, (Len - I) * Typ.Arr_El.W),
+ (Sig_Index (Sig, (I - 1) * Typ.Arr_El.W),
Val + Size_Type (I - 1) * Typ.Arr_El.Sz,
- Sig_Index (Pfx, (Len - I) * Typ.Arr_El.W),
+ Sig_Index (Pfx, (I - 1) * Typ.Arr_El.W),
Typ.Arr_El, Time);
end loop;
end;
@@ -3094,7 +3094,7 @@ package body Simul.Vhdl_Simul is
begin
for I in 1 .. Len loop
Register_Prefix
- (Typ.Arr_El, Sig_Index (Sig, (Len - I) * Typ.Arr_El.W));
+ (Typ.Arr_El, Sig_Index (Sig, (I - 1) * Typ.Arr_El.W));
end loop;
end;
when Type_Record =>
@@ -3196,7 +3196,7 @@ package body Simul.Vhdl_Simul is
begin
for I in 1 .. Len loop
Set_Disconnect (Typ.Arr_El,
- Sig_Index (Sig, (Len - I) * Typ.Arr_El.W),
+ Sig_Index (Sig, (I - 1) * Typ.Arr_El.W),
Val);
end loop;
end;
@@ -3247,9 +3247,9 @@ package body Simul.Vhdl_Simul is
begin
for I in 1 .. Len loop
Add_Extra_Driver_To_Signal
- (Sig_Index (Sig, (Len - I) * El.W), El,
+ (Sig_Index (Sig, (I - 1) * El.W), El,
Init + Size_Type (I - 1) * El.Sz,
- Off + (Len - I) * El.W, Vec);
+ Off + (I - 1) * El.W, Vec);
end loop;
end;
when Type_Record =>
@@ -3320,9 +3320,9 @@ package body Simul.Vhdl_Simul is
raise Internal_Error;
end if;
for I in 1 .. Len loop
- Connect ((Etyp, Sig_Index (Dst.Mem, (Len - I) * Etyp.W)),
+ Connect ((Etyp, Sig_Index (Dst.Mem, (I - 1) * Etyp.W)),
(Src.Typ.Arr_El,
- Sig_Index (Src.Mem, (Len - I) * Etyp.W)),
+ Sig_Index (Src.Mem, (I - 1) * Etyp.W)),
Mode);
end loop;
end;
@@ -3380,7 +3380,7 @@ package body Simul.Vhdl_Simul is
begin
for I in 1 .. Len loop
Create_Shadow_Signal
- (Sig_Index (Sig, (Len - I) * Typ.Arr_El.W),
+ (Sig_Index (Sig, (I - 1) * Typ.Arr_El.W),
Val + Size_Type (I - 1) * Typ.Arr_El.Sz,
Typ.Arr_El);
end loop;
@@ -3476,9 +3476,7 @@ package body Simul.Vhdl_Simul is
return Read_Sig (Sig);
when Type_Vector
| Type_Array =>
- return Get_Leftest_Signal
- (Sig_Index (Sig, (Typ.Abound.Len - 1) * Typ.Arr_El.W),
- Typ.Arr_El);
+ return Get_Leftest_Signal (Sig, Typ.Arr_El);
when Type_Record =>
declare
E : Rec_El_Type renames Typ.Rec.E (1);
@@ -3628,7 +3626,7 @@ package body Simul.Vhdl_Simul is
begin
for I in 1 .. Len loop
Signal_Associate_Cst
- (Sig_Index (Sig, (Len - I) * Typ.Arr_El.W),
+ (Sig_Index (Sig, (I - 1) * Typ.Arr_El.W),
Typ.Arr_El,
Val + Size_Type (I - 1) * Typ.Arr_El.Sz);
end loop;
@@ -3690,7 +3688,7 @@ package body Simul.Vhdl_Simul is
begin
for I in 1 .. Len loop
Update_Sig_Val (El,
- Sig_Index (Sigs, (Len - I) * El.W),
+ Sig_Index (Sigs, (I - 1) * El.W),
Vals + Size_Type (I - 1) * El.Sz);
end loop;
end;
diff --git a/src/synth/elab-vhdl_expr.adb b/src/synth/elab-vhdl_expr.adb
index c43e3808e..2ef7d8982 100644
--- a/src/synth/elab-vhdl_expr.adb
+++ b/src/synth/elab-vhdl_expr.adb
@@ -484,8 +484,8 @@ package body Elab.Vhdl_Expr is
begin
Pfx_Typ := Exec_Name_Subtype (Syn_Inst, Get_Prefix (Name));
Get_Onedimensional_Array_Bounds (Pfx_Typ, Pfx_Bnd, El_Typ);
- Synth_Slice_Suffix (Syn_Inst, Name, Pfx_Bnd, El_Typ,
- Res_Bnd, Inp, Sl_Off, Err);
+ Synth_Slice_Suffix (Syn_Inst, Name, Pfx_Bnd, Pfx_Typ.Wkind,
+ El_Typ, Res_Bnd, Inp, Sl_Off, Err);
if Err then
return null;
end if;
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb
index d1d705592..80d1a22fc 100644
--- a/src/synth/synth-vhdl_expr.adb
+++ b/src/synth/synth-vhdl_expr.adb
@@ -838,9 +838,11 @@ package body Synth.Vhdl_Expr is
-- Convert index IDX in PFX to an offset.
-- SYN_INST and LOC are used in case of error.
- function Index_To_Offset
- (Syn_Inst : Synth_Instance_Acc; Bnd : Bound_Type; Idx : Int64; Loc : Node)
- return Value_Offsets
+ function Index_To_Offset (Syn_Inst : Synth_Instance_Acc;
+ Bnd : Bound_Type;
+ Order : Wkind_Type;
+ Idx : Int64;
+ Loc : Node) return Value_Offsets
is
Res : Value_Offsets;
begin
@@ -852,10 +854,22 @@ package body Synth.Vhdl_Expr is
-- The offset is from the LSB (bit 0). Bit 0 is the rightmost one.
case Bnd.Dir is
when Dir_To =>
- Res.Net_Off := Uns32 (Bnd.Right - Int32 (Idx));
+ case Order is
+ when Wkind_Undef
+ | Wkind_Net =>
+ Res.Net_Off := Uns32 (Bnd.Right - Int32 (Idx));
+ when Wkind_Sim =>
+ Res.Net_Off := Uns32 (Int32 (Idx) - Bnd.Left);
+ end case;
Res.Mem_Off := Size_Type (Int32 (Idx) - Bnd.Left);
when Dir_Downto =>
- Res.Net_Off := Uns32 (Int32 (Idx) - Bnd.Right);
+ case Order is
+ when Wkind_Undef
+ | Wkind_Net =>
+ Res.Net_Off := Uns32 (Int32 (Idx) - Bnd.Right);
+ when Wkind_Sim =>
+ Res.Net_Off := Uns32 (Bnd.Left - Int32 (Idx));
+ end case;
Res.Mem_Off := Size_Type (Bnd.Left - Int32 (Idx));
end case;
@@ -945,7 +959,8 @@ package body Synth.Vhdl_Expr is
Bound_Error (Syn_Inst, Idx_Expr, Bnd, Int32 (Idx));
Error := True;
else
- Idx_Off := Index_To_Offset (Syn_Inst, Bnd, Idx, Idx_Expr);
+ Idx_Off := Index_To_Offset (Syn_Inst, Bnd, Arr_Typ.Wkind,
+ Idx, Idx_Expr);
Off.Net_Off := Off.Net_Off
+ Idx_Off.Net_Off * Stride * El_Typ.W;
Off.Mem_Off := Off.Mem_Off
@@ -1227,6 +1242,7 @@ package body Synth.Vhdl_Expr is
Expr : Node;
Name : Node;
Pfx_Bnd : Bound_Type;
+ Order : Wkind_Type;
L, R : Int64;
Dir : Direction_Type;
El_Typ : Type_Acc;
@@ -1277,11 +1293,27 @@ package body Synth.Vhdl_Expr is
case Pfx_Bnd.Dir is
when Dir_To =>
Len := Uns32 (R - L + 1);
- Off.Net_Off := Uns32 (Pfx_Bnd.Right - Int32 (R)) * El_Typ.W;
+ case Order is
+ when Wkind_Undef
+ | Wkind_Net =>
+ Off.Net_Off :=
+ Uns32 (Pfx_Bnd.Right - Int32 (R)) * El_Typ.W;
+ when Wkind_Sim =>
+ Off.Net_Off :=
+ Uns32 (Int32 (L) - Pfx_Bnd.Left) * El_Typ.W;
+ end case;
Off.Mem_Off := Size_Type (Int32 (L) - Pfx_Bnd.Left) * El_Typ.Sz;
when Dir_Downto =>
Len := Uns32 (L - R + 1);
- Off.Net_Off := Uns32 (Int32 (R) - Pfx_Bnd.Right) * El_Typ.W;
+ case Order is
+ when Wkind_Undef
+ | Wkind_Net =>
+ Off.Net_Off :=
+ Uns32 (Int32 (R) - Pfx_Bnd.Right) * El_Typ.W;
+ when Wkind_Sim =>
+ Off.Net_Off :=
+ Uns32 (Pfx_Bnd.Left - Int32 (L)) * El_Typ.W;
+ end case;
Off.Mem_Off := Size_Type (Pfx_Bnd.Left - Int32 (L)) * El_Typ.Sz;
end case;
end if;
@@ -1295,6 +1327,7 @@ package body Synth.Vhdl_Expr is
procedure Synth_Slice_Suffix (Syn_Inst : Synth_Instance_Acc;
Name : Node;
Pfx_Bnd : Bound_Type;
+ Order : Wkind_Type;
El_Typ : Type_Acc;
Res_Bnd : out Bound_Type;
Inp : out Net;
@@ -1325,7 +1358,7 @@ package body Synth.Vhdl_Expr is
begin
Synth_Discrete_Range (Syn_Inst, Expr, Rng);
Synth_Slice_Const_Suffix (Syn_Inst, Expr,
- Name, Pfx_Bnd,
+ Name, Pfx_Bnd, Order,
Rng.Left, Rng.Right, Rng.Dir,
El_Typ, Res_Bnd, Off, Error);
return;
@@ -1334,7 +1367,7 @@ package body Synth.Vhdl_Expr is
if Is_Static_Val (Left.Val) and then Is_Static_Val (Right.Val) then
Synth_Slice_Const_Suffix (Syn_Inst, Expr,
- Name, Pfx_Bnd,
+ Name, Pfx_Bnd, Order,
Get_Static_Discrete (Left),
Get_Static_Discrete (Right),
Dir,
diff --git a/src/synth/synth-vhdl_expr.ads b/src/synth/synth-vhdl_expr.ads
index cdffd0f68..6bd109c73 100644
--- a/src/synth/synth-vhdl_expr.ads
+++ b/src/synth/synth-vhdl_expr.ads
@@ -119,6 +119,7 @@ package Synth.Vhdl_Expr is
procedure Synth_Slice_Suffix (Syn_Inst : Synth_Instance_Acc;
Name : Node;
Pfx_Bnd : Bound_Type;
+ Order : Wkind_Type;
El_Typ : Type_Acc;
Res_Bnd : out Bound_Type;
Inp : out Net;
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index 78a177359..1cc9e24a8 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -188,7 +188,7 @@ package body Synth.Vhdl_Stmts is
end if;
Get_Onedimensional_Array_Bounds (Dest_Typ, Pfx_Bnd, El_Typ);
- Synth_Slice_Suffix (Syn_Inst, Pfx, Pfx_Bnd, El_Typ,
+ Synth_Slice_Suffix (Syn_Inst, Pfx, Pfx_Bnd, Dest_Typ.Wkind, El_Typ,
Res_Bnd, Sl_Voff, Sl_Off, Err);
if Err then
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-02 05:06:05 +0000