2 files changed, 53 insertions, 0 deletions
diff --git a/testsuite/synth/issue1047/testsuite.sh b/testsuite/synth/issue1047/testsuite.sh
new file mode 100755
index 000000000..4ff5449d8
--- /dev/null
+++ b/testsuite/synth/issue1047/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in top; do
+  synth $t.vhdl -e $t > syn_$t.vhdl
+#  analyze syn_$t.vhdl
+done
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1047/top.vhdl b/testsuite/synth/issue1047/top.vhdl
new file mode 100644
index 000000000..dcdb44524
--- /dev/null
+++ b/testsuite/synth/issue1047/top.vhdl
@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.ALL;
+
+entity child is
+  port (
+    A:  out std_logic
+  );
+end entity child;
+
+architecture rtl of child is
+begin
+  A <= '0';
+end architecture rtl;
+
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+
+entity top is
+  port (
+    A:  out std_logic_vector(1 downto 0)
+  );
+end entity top;
+
+architecture rtl of top is
+  component child is
+    port (
+      A:  out std_logic
+    );
+  end component child;
+
+  constant N:   integer := 2;
+begin
+  CHILDGEN: for i in 0 to N-1 generate
+  begin
+    CHILDINST : child
+      port map(
+        A => A(i)
+      );
+  end generate CHILDGEN;
+end architecture rtl;