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-rw-r--r--src/grt/grt-fst.adb18
-rw-r--r--src/grt/grt-vcd.adb47
-rw-r--r--src/grt/grt-vcd.ads13
-rw-r--r--src/grt/grt-vpi.adb112
-rw-r--r--src/grt/grt-vpi.ads29
5 files changed, 142 insertions, 77 deletions
diff --git a/src/grt/grt-fst.adb b/src/grt/grt-fst.adb
index 7f5444e08..199952060 100644
--- a/src/grt/grt-fst.adb
+++ b/src/grt/grt-fst.adb
@@ -233,7 +233,9 @@ package body Grt.Fst is
Get_Verilog_Wire (Sig, Vcd_El);
case Vcd_El.Vtype is
- when Vcd_Bad =>
+ when Vcd_Bad
+ | Vcd_Array
+ | Vcd_Struct =>
-- Not handled.
return;
when Vcd_Enum8 =>
@@ -262,11 +264,11 @@ package body Grt.Fst is
Sdt := FST_SDT_VHDL_STD_LOGIC;
when Vcd_Bitvector =>
Vt := FST_VT_VCD_REG;
- Len := Interfaces.C.unsigned (Vcd_El.Irange.I32.Len);
+ Len := Interfaces.C.unsigned (Vcd_El.Vec_Range.I32.Len);
Sdt := FST_SDT_VHDL_BIT_VECTOR;
when Vcd_Stdlogic_Vector =>
Vt := FST_VT_VCD_REG;
- Len := Interfaces.C.unsigned (Vcd_El.Irange.I32.Len);
+ Len := Interfaces.C.unsigned (Vcd_El.Vec_Range.I32.Len);
Sdt := FST_SDT_VHDL_STD_LOGIC_VECTOR;
end case;
@@ -374,13 +376,13 @@ package body Grt.Fst is
end Append;
begin
Vhpi_Get_Str (VhpiNameP, Sig, Name2, Name_Len);
- if Vcd_El.Irange /= null then
+ if Vcd_El.Vec_Range /= null then
Name2 (Name_Len + 1) := '[';
Name_Len := Name_Len + 1;
- Append (Vcd_El.Irange.I32.Left);
+ Append (Vcd_El.Vec_Range.I32.Left);
Name2 (Name_Len + 1) := ':';
Name_Len := Name_Len + 1;
- Append (Vcd_El.Irange.I32.Right);
+ Append (Vcd_El.Vec_Range.I32.Right);
Name2 (Name_Len + 1) := ']';
Name_Len := Name_Len + 1;
end if;
@@ -610,7 +612,9 @@ package body Grt.Fst is
null;
when Vcd_Enum8 =>
Fst_Put_Enum8 (Hand, Verilog_Wire_Val (V.Wire).E8, V.Wire.Rti);
- when Vcd_Bad =>
+ when Vcd_Bad
+ | Vcd_Array
+ | Vcd_Struct =>
null;
end case;
end Fst_Put_Var;
diff --git a/src/grt/grt-vcd.adb b/src/grt/grt-vcd.adb
index 0d39b6620..ff0d69424 100644
--- a/src/grt/grt-vcd.adb
+++ b/src/grt/grt-vcd.adb
@@ -300,8 +300,8 @@ package body Grt.Vcd is
end case;
end Rti_To_Vcd_Kind;
- function Rti_To_Vcd_Kind (Rti : Ghdl_Rtin_Type_Array_Acc)
- return Vcd_Var_Type
+ function Rti_Array_To_Vcd_Kind (Rti : Ghdl_Rtin_Type_Array_Acc)
+ return Vcd_Var_Type
is
It : Ghdl_Rti_Access;
begin
@@ -329,9 +329,9 @@ package body Grt.Vcd is
when Vcd_Stdlogic =>
return Vcd_Stdlogic_Vector;
when others =>
- return Vcd_Bad;
+ return Vcd_Array;
end case;
- end Rti_To_Vcd_Kind;
+ end Rti_Array_To_Vcd_Kind;
procedure Get_Verilog_Wire (Sig : VhpiHandleT; Info : out Verilog_Wire_Info)
is
@@ -373,7 +373,7 @@ package body Grt.Vcd is
Idx_Rti : constant Ghdl_Rti_Access :=
Get_Base_Type (Arr_Rti.Indexes (0));
begin
- Kind := Rti_To_Vcd_Kind (Arr_Rti);
+ Kind := Rti_Array_To_Vcd_Kind (Arr_Rti);
Bounds := Loc_To_Addr (St.Common.Depth, St.Layout,
Avhpi_Get_Context (Sig));
Bounds := Array_Layout_To_Bounds (Bounds);
@@ -386,7 +386,7 @@ package body Grt.Vcd is
Idx_Rti : constant Ghdl_Rti_Access :=
Get_Base_Type (Arr_Rti.Indexes (0));
begin
- Kind := Rti_To_Vcd_Kind (Arr_Rti);
+ Kind := Rti_Array_To_Vcd_Kind (Arr_Rti);
Extract_Range (Bounds, Idx_Rti, Irange);
end;
when others =>
@@ -426,7 +426,8 @@ package body Grt.Vcd is
end case;
case Kind is
- when Vcd_Bad =>
+ when Vcd_Bad
+ | Vcd_Struct =>
Info := (Vcd_Bad, Vcd_Effective, Null_Address);
when Vcd_Enum8 =>
Info := (Vcd_Enum8, Val, Sig_Addr, Rti);
@@ -444,6 +445,8 @@ package body Grt.Vcd is
Info := (Vcd_Bitvector, Val, Sig_Addr, Irange);
when Vcd_Stdlogic_Vector =>
Info := (Vcd_Stdlogic_Vector, Val, Sig_Addr, Irange);
+ when Vcd_Array =>
+ Info := (Vcd_Array, Val, Sig_Addr, Rti, Bounds);
end case;
end Get_Verilog_Wire;
@@ -451,7 +454,7 @@ package body Grt.Vcd is
return Ghdl_Index_Type is
begin
if Info.Vtype in Vcd_Var_Vectors then
- return Info.Irange.I32.Len;
+ return Info.Vec_Range.I32.Len;
else
return 1;
end if;
@@ -519,8 +522,10 @@ package body Grt.Vcd is
when Vcd_Bitvector
| Vcd_Stdlogic_Vector =>
Vcd_Put ("reg ");
- Vcd_Put_I32 (Ghdl_I32 (Vcd_El.Irange.I32.Len));
+ Vcd_Put_I32 (Ghdl_I32 (Vcd_El.Vec_Range.I32.Len));
when Vcd_Bad
+ | Vcd_Array
+ | Vcd_Struct
| Vcd_Enum8 =>
null;
end case;
@@ -530,9 +535,9 @@ package body Grt.Vcd is
Vcd_Put_Name (Sig);
if Vcd_El.Vtype in Vcd_Var_Vectors then
Vcd_Putc ('[');
- Vcd_Put_I32 (Vcd_El.Irange.I32.Left);
+ Vcd_Put_I32 (Vcd_El.Vec_Range.I32.Left);
Vcd_Putc (':');
- Vcd_Put_I32 (Vcd_El.Irange.I32.Right);
+ Vcd_Put_I32 (Vcd_El.Vec_Range.I32.Right);
Vcd_Putc (']');
end if;
Vcd_Putc (' ');
@@ -734,6 +739,8 @@ package body Grt.Vcd is
end loop;
Vcd_Putc (' ');
when Vcd_Bad
+ | Vcd_Array
+ | Vcd_Struct
| Vcd_Enum8 =>
null;
end case;
@@ -758,12 +765,14 @@ package body Grt.Vcd is
end if;
when Vcd_Bitvector
| Vcd_Stdlogic_Vector =>
- for J in 0 .. Info.Irange.I32.Len - 1 loop
+ for J in 0 .. Info.Vec_Range.I32.Len - 1 loop
if To_Signal_Arr_Ptr (Info.Ptr)(J).Last_Event = Last then
return True;
end if;
end loop;
- when Vcd_Bad =>
+ when Vcd_Bad
+ | Vcd_Array
+ | Vcd_Struct =>
null;
end case;
when Vcd_Driving =>
@@ -779,12 +788,14 @@ package body Grt.Vcd is
end if;
when Vcd_Bitvector
| Vcd_Stdlogic_Vector =>
- for J in 0 .. Info.Irange.I32.Len - 1 loop
+ for J in 0 .. Info.Vec_Range.I32.Len - 1 loop
if To_Signal_Arr_Ptr (Info.Ptr)(J).Last_Active = Last then
return True;
end if;
end loop;
- when Vcd_Bad =>
+ when Vcd_Bad
+ | Vcd_Array
+ | Vcd_Struct =>
null;
end case;
end case;
@@ -805,12 +816,14 @@ package body Grt.Vcd is
end if;
when Vcd_Bitvector
| Vcd_Stdlogic_Vector =>
- for J in 0 .. Info.Irange.I32.Len - 1 loop
+ for J in 0 .. Info.Vec_Range.I32.Len - 1 loop
if To_Signal_Arr_Ptr (Info.Ptr)(J).Event then
return True;
end if;
end loop;
- when Vcd_Bad =>
+ when Vcd_Bad
+ | Vcd_Array
+ | Vcd_Struct =>
null;
end case;
return False;
diff --git a/src/grt/grt-vcd.ads b/src/grt/grt-vcd.ads
index 6e76f3c75..5ab3b7636 100644
--- a/src/grt/grt-vcd.ads
+++ b/src/grt/grt-vcd.ads
@@ -58,7 +58,13 @@ package Grt.Vcd is
Vcd_Bit, Vcd_Stdlogic,
-- A bit vector type
- Vcd_Bitvector, Vcd_Stdlogic_Vector
+ Vcd_Bitvector, Vcd_Stdlogic_Vector,
+
+ -- Any array (that is not a vector)
+ Vcd_Array,
+
+ -- Any record
+ Vcd_Struct
);
subtype Vcd_Var_Vectors is Vcd_Var_Type
@@ -80,10 +86,13 @@ package Grt.Vcd is
case Vtype is
when Vcd_Var_Vectors =>
-- Vector bounds.
- Irange : Ghdl_Range_Ptr;
+ Vec_Range : Ghdl_Range_Ptr;
when Vcd_Enum8 =>
-- Base type.
Rti : Rtis.Ghdl_Rti_Access;
+ when Vcd_Array =>
+ Arr_Rti : Rtis.Ghdl_Rti_Access;
+ Arr_Layout : System.Address;
when others =>
null;
end case;
diff --git a/src/grt/grt-vpi.adb b/src/grt/grt-vpi.adb
index 3577b08ff..4b8ee9b91 100644
--- a/src/grt/grt-vpi.adb
+++ b/src/grt/grt-vpi.adb
@@ -212,6 +212,8 @@ package body Grt.Vpi is
Trace ("vpiModule");
when vpiNet =>
Trace ("vpiNet");
+ when vpiNetArray =>
+ Trace ("vpiNetArray");
when vpiPort =>
Trace ("vpiPort");
when vpiParameter =>
@@ -224,6 +226,8 @@ package body Grt.Vpi is
Trace ("vpiLeftRange");
when vpiRightRange =>
Trace ("vpiRightRange");
+ when vpiRange =>
+ Trace ("vpiRange");
when vpiStop =>
Trace ("vpiStop");
@@ -449,11 +453,12 @@ package body Grt.Vpi is
begin
Get_Verilog_Wire (Ref.Ref, Info);
case Info.Vtype is
- when Vcd_Var_Vectors =>
+ when Vcd_Var_Vectors
+ | Vcd_Array =>
return Natural (Get_Wire_Length (Info));
when Vcd_Bool
- | Vcd_Bit
- | Vcd_Stdlogic =>
+ | Vcd_Bit
+ | Vcd_Stdlogic =>
return 1;
when Vcd_Integer32 =>
return 32;
@@ -461,7 +466,8 @@ package body Grt.Vpi is
return 8;
when Vcd_Float64 =>
return 0;
- when Vcd_Bad =>
+ when Vcd_Bad
+ | Vcd_Struct =>
return 0;
end case;
end Vpi_Get_Size;
@@ -482,7 +488,9 @@ package body Grt.Vpi is
when Vcd_Bitvector
| Vcd_Stdlogic_Vector =>
return True;
- when Vcd_Bad =>
+ when Vcd_Bad
+ | Vcd_Struct
+ | Vcd_Array =>
return False;
end case;
end Vpi_Get_Vector;
@@ -547,23 +555,27 @@ package body Grt.Vpi is
| VhpiForGenerateK
| VhpiCompInstStmtK =>
return vpiModule;
- when VhpiPortDeclK =>
- declare
- Info : Verilog_Wire_Info;
- begin
- Get_Verilog_Wire (Res, Info);
- if Info.Vtype /= Vcd_Bad then
- return vpiNet;
- end if;
- end;
- when VhpiSigDeclK =>
+ when VhpiPortDeclK
+ | VhpiSigDeclK =>
declare
Info : Verilog_Wire_Info;
begin
Get_Verilog_Wire (Res, Info);
- if Info.Vtype /= Vcd_Bad then
- return vpiNet;
- end if;
+ case Info.Vtype is
+ when Vcd_Enum8
+ | Vcd_Bool
+ | Vcd_Var_Vectors
+ | Vcd_Integer32
+ | Vcd_Bit
+ | Vcd_Stdlogic =>
+ return vpiNet;
+ when Vcd_Array =>
+ return vpiNetArray;
+ when Vcd_Bad
+ | Vcd_Struct
+ | Vcd_Float64 =>
+ return vpiUndefined;
+ end case;
end;
when VhpiGenericDeclK =>
declare
@@ -599,6 +611,9 @@ package body Grt.Vpi is
when vpiNet =>
return new struct_vpiHandle'(mType => vpiNet,
Ref => Res);
+ when vpiNetArray =>
+ return new struct_vpiHandle'(mType => vpiNetArray,
+ Ref => Res);
when vpiPort =>
return new struct_vpiHandle'(mType => vpiPort,
Ref => Res);
@@ -794,9 +809,11 @@ package body Grt.Vpi is
return null;
end case;
when vpiRightRange
- | vpiLeftRange =>
+ | vpiLeftRange =>
case Ref.mType is
- when vpiPort| vpiNet =>
+ when vpiPort
+ | vpiNet
+ | vpiNetArray =>
Res := new struct_vpiHandle (aType);
Res.Ref := Ref.Ref;
return Res;
@@ -880,17 +897,14 @@ package body Grt.Vpi is
-- Get verilog compat info.
Get_Verilog_Wire (Obj, Info);
- if Info.Vtype = Vcd_Bad then
- return null;
- end if;
-
- Len := Get_Wire_Length (Info);
Reset (Buf_Value); -- reset string buffer
case Info.Vtype is
when Vcd_Bad
- | Vcd_Float64 =>
+ | Vcd_Float64
+ | Vcd_Array
+ | Vcd_Struct =>
return null;
when Vcd_Enum8 =>
declare
@@ -910,12 +924,14 @@ package body Grt.Vpi is
| Vcd_Bool =>
Append (Buf_Value, Map_Std_B1 (Verilog_Wire_Val (Info).B1));
when Vcd_Bitvector =>
+ Len := Get_Wire_Length (Info);
for J in 0 .. Len - 1 loop
Append (Buf_Value, Map_Std_B1 (Verilog_Wire_Val (Info, J).B1));
end loop;
when Vcd_Stdlogic =>
Append (Buf_Value, E8_To_Char (Verilog_Wire_Val (Info).E8));
when Vcd_Stdlogic_Vector =>
+ Len := Get_Wire_Length (Info);
for J in 0 .. Len - 1 loop
Append (Buf_Value, E8_To_Char (Verilog_Wire_Val (Info, J).E8));
end loop;
@@ -924,6 +940,22 @@ package body Grt.Vpi is
return Get_C_String (Buf_Value);
end ii_vpi_get_value_bin_str;
+ function Vpi_Get_Value_Range (Expr : vpiHandle) return Integer
+ is
+ Info : Verilog_Wire_Info;
+ begin
+ Get_Verilog_Wire (Expr.Ref, Info);
+ if Info.Vec_Range /= null then
+ if Expr.mType = vpiLeftRange then
+ return Integer (Info.Vec_Range.I32.Left);
+ else
+ return Integer (Info.Vec_Range.I32.Right);
+ end if;
+ else
+ return 0;
+ end if;
+ end Vpi_Get_Value_Range;
+
procedure vpi_get_value (Expr : vpiHandle; Value : p_vpi_value) is
begin
if Flag_Trace then
@@ -957,21 +989,8 @@ package body Grt.Vpi is
when vpiIntVal=>
case Expr.mType is
when vpiLeftRange
- | vpiRightRange=>
- declare
- Info : Verilog_Wire_Info;
- begin
- Get_Verilog_Wire (Expr.Ref, Info);
- if Info.Irange /= null then
- if Expr.mType = vpiLeftRange then
- Value.Integer_m := Integer (Info.Irange.I32.Left);
- else
- Value.Integer_m := Integer (Info.Irange.I32.Right);
- end if;
- else
- Value.Integer_m := 0;
- end if;
- end;
+ | vpiRightRange=>
+ Value.Integer_m := Vpi_Get_Value_Range (Expr);
when others=>
dbgPut_Line ("vpi_get_value: vpiIntVal, unknown mType");
end case;
@@ -1001,7 +1020,9 @@ package body Grt.Vpi is
Vec : Std_Ulogic_Array) is
begin
case Info.Vtype is
- when Vcd_Bad =>
+ when Vcd_Bad
+ | Vcd_Array
+ | Vcd_Struct =>
return;
when Vcd_Bit
| Vcd_Bool
@@ -1223,8 +1244,11 @@ package body Grt.Vpi is
-- Convert LEN (number of elements) to number of bits.
case Info.Vtype is
- when Vcd_Bad =>
- null;
+ when Vcd_Bad
+ | Vcd_Array
+ | Vcd_Struct =>
+ dbgPut_Line ("vpi_put_value: bad object kind");
+ return null;
when Vcd_Bit
| Vcd_Bool
| Vcd_Bitvector
diff --git a/src/grt/grt-vpi.ads b/src/grt/grt-vpi.ads
index 44be9eefe..187dcbfdd 100644
--- a/src/grt/grt-vpi.ads
+++ b/src/grt/grt-vpi.ads
@@ -27,8 +27,7 @@ with Grt.Vcd;
with Grt.Callbacks;
package Grt.Vpi is
-
- -- Properties, see vpi_user.h
+ -- Properties and objects, see vpi_user.h
vpiUndefined : constant Integer := -1;
vpiType : constant Integer := 1;
vpiName : constant Integer := 2;
@@ -45,11 +44,6 @@ package Grt.Vpi is
vpiScalar : constant Integer := 17;
vpiVector : constant Integer := 18;
- -- object codes, see vpi_user.h
- vpiModule : constant Integer := 32;
- vpiNet : constant Integer := 36;
- vpiPort : constant Integer := 44;
- --
vpiDirection : constant Integer := 20;
vpiInput : constant Integer := 1;
vpiOutput : constant Integer := 2;
@@ -57,12 +51,33 @@ package Grt.Vpi is
vpiMixedIO : constant Integer := 4;
vpiNoDirection : constant Integer := 5;
+ vpiIntegerVar : constant Integer := 25;
+ vpiMemory : constant Integer := 29;
+ vpiModPath : constant Integer := 31;
+ vpiModule : constant Integer := 32;
+ vpiNamedEvent : constant Integer := 34;
+ vpiNet : constant Integer := 36;
vpiParameter : constant Integer := 41;
+ vpiPort : constant Integer := 44;
+ vpiRealVar : constant Integer := 47;
+ vpiReg : constant Integer := 48;
+ vpiTchk : constant Integer := 61;
+
vpiLeftRange : constant Integer := 79;
vpiRightRange : constant Integer := 83;
vpiScope : constant Integer := 84;
vpiInternalScope : constant Integer := 92;
+ vpiProcess : constant Integer := 92;
+
+ vpiPrimitive : constant Integer := 103;
+ vpiAttribute : constant Integer := 105;
+ vpiPrimitiveArray : constant Integer := 113;
+ vpiNetArray : constant Integer := 114;
+ vpiRange : constant Integer := 115;
+ vpiRegArray : constant Integer := 116;
+ vpiNamedEventArray : constant Integer := 129;
+ -- vpi_control constants.
vpiStop : constant := 66;
vpiFinish : constant := 67;
vpiReset : constant := 68;
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-25 14:42:31 +0000