diff options
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 7 | ||||
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 3 |
2 files changed, 7 insertions, 3 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 8480432a6..77f3bc0b3 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -618,7 +618,8 @@ package body Simul.Vhdl_Elab is Gather_Sensitivity (Inst, Proc_Idx, List); return; end if; - when Iir_Kind_Psl_Assert_Directive => + when Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Cover_Directive => List := Get_PSL_Clock_Sensitivity (Proc); Gather_Sensitivity (Inst, Proc_Idx, List); return; @@ -903,9 +904,11 @@ package body Simul.Vhdl_Elab is Gather_Process_Drivers (Inst, Stmt, Processes_Table.Last); pragma Assert (Is_Expr_Pool_Empty); Gather_Process_Sensitivity (Inst, Stmt, Processes_Table.Last); - when Iir_Kind_Psl_Default_Clock => + when Iir_Kind_Psl_Default_Clock + | Iir_Kind_Psl_Declaration => null; when Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Concurrent_Break_Statement => Processes_Table.Append ((Proc => Stmt, Inst => Inst, diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index df958a43c..90156b763 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2229,7 +2229,8 @@ package body Simul.Vhdl_Simul is end if; Create_Process_Drivers (I); - when Iir_Kind_Psl_Assert_Directive => + when Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Cover_Directive => Processes_State (I) := (Kind => Kind_PSL, Has_State => False, Top_Instance => Instance, |