diff options
| -rw-r--r-- | pyGHDL/dom/DesignUnit.py | 1 | ||||
| -rw-r--r-- | pyGHDL/dom/__init__.py | 1 | ||||
| -rw-r--r-- | pyGHDL/requirements.txt | 4 |
3 files changed, 3 insertions, 3 deletions
diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index a8249d38d..c4f19deef 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -59,6 +59,7 @@ from pyVHDLModel.VHDLModel import ( PortInterfaceItem, EntityOrSymbol, Name, + ConcurrentStatement, ) from pyGHDL.libghdl.vhdl import nodes diff --git a/pyGHDL/dom/__init__.py b/pyGHDL/dom/__init__.py index 19f23a94b..d3dc506f5 100644 --- a/pyGHDL/dom/__init__.py +++ b/pyGHDL/dom/__init__.py @@ -46,7 +46,6 @@ __all__ = [] @export class Position: """Represents the source code position of a IIR node in a source file.""" - _filename: Path _line: int _column: int diff --git a/pyGHDL/requirements.txt b/pyGHDL/requirements.txt index 974fef2ed..d09e07a4a 100644 --- a/pyGHDL/requirements.txt +++ b/pyGHDL/requirements.txt @@ -1,3 +1,3 @@ pydecor>=2.0.1 -pyVHDLModel==0.10.4 -#https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel +#pyVHDLModel==0.10.5 +https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel |