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-rw-r--r--pyGHDL/dom/Concurrent.py48
-rw-r--r--pyGHDL/dom/_Translate.py34
-rw-r--r--testsuite/pyunit/Current.vhdl32
3 files changed, 73 insertions, 41 deletions
diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py
index 80417c07b..2698054e5 100644
--- a/pyGHDL/dom/Concurrent.py
+++ b/pyGHDL/dom/Concurrent.py
@@ -39,53 +39,65 @@ from pyVHDLModel.SyntaxModel import (
ComponentInstantiation as VHDLModel_ComponentInstantiation,
EntityInstantiation as VHDLModel_EntityInstantiation,
ConfigurationInstantiation as VHDLModel_ConfigurationInstantiation,
- PortInterfaceItem,
- ConcurrentStatement,
+ ConcurrentStatement, Name,
)
from pyGHDL.libghdl import Iir
from pyGHDL.libghdl.vhdl import nodes
from pyGHDL.dom import DOMMixin
-from pyGHDL.dom.Symbol import EntitySymbol
+from pyGHDL.dom._Utils import GetNameOfNode
@export
class ComponentInstantiation(VHDLModel_ComponentInstantiation, DOMMixin):
- def __init__(self, node: Iir, componentName: str):
- super().__init__(componentName)
+ def __init__(self, node: Iir, label: str, componentName: Name):
+ super().__init__(label, componentName)
DOMMixin.__init__(self, node)
@classmethod
- def parse(cls, instantiationNode: Iir) -> "ComponentInstantiation":
- componentName = ""
+ def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ComponentInstantiation":
+ from pyGHDL.dom._Translate import GetNameFromNode
- return cls(instantiationNode, componentName)
+ componentName = GetNameFromNode(instantiatedUnit)
+
+ return cls(instantiationNode, label, componentName)
@export
class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin):
- def __init__(self, node: Iir, entityName: EntitySymbol):
- super().__init__(entityName)
+ def __init__(self, node: Iir, label: str, entityName: Name, architectureName: Name = None):
+ super().__init__(label, entityName, architectureName)
DOMMixin.__init__(self, node)
@classmethod
- def parse(cls, instantiationNode: Iir) -> "EntityInstantiation":
- entityName = ""
+ def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "EntityInstantiation":
+ from pyGHDL.dom._Translate import GetNameFromNode
+
+ entityId = nodes.Get_Entity_Name(instantiatedUnit)
+ entityName = GetNameFromNode(entityId)
- return cls(instantiationNode, entityName)
+ architectureName = None
+ architectureId = nodes.Get_Architecture(instantiatedUnit)
+ if architectureId != nodes.Null_Iir:
+ architectureName = GetNameOfNode(architectureId)
+
+ return cls(instantiationNode, label, entityName, architectureName)
@export
class ConfigurationInstantiation(VHDLModel_ConfigurationInstantiation, DOMMixin):
- def __init__(self, node: Iir, configurationName: str):
- super().__init__(configurationName)
+ def __init__(self, node: Iir, label: str, configurationName: Name):
+ super().__init__(label, configurationName)
DOMMixin.__init__(self, node)
@classmethod
- def parse(cls, instantiationNode: Iir) -> "ConfigurationInstantiation":
- configurationName = ""
+ def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ConfigurationInstantiation":
+ from pyGHDL.dom._Translate import GetNameFromNode
+
+ configurationId = nodes.Get_Configuration_Name(instantiatedUnit)
+ configurationName = GetNameFromNode(configurationId)
- return cls(instantiationNode, configurationName)
+ return cls(instantiationNode, label, configurationName)
@export
diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py
index 84b99a4a3..b7e8f5ab9 100644
--- a/pyGHDL/dom/_Translate.py
+++ b/pyGHDL/dom/_Translate.py
@@ -138,7 +138,7 @@ from pyGHDL.dom.Expression import (
MatchingLessEqualExpression,
MatchingGreaterThanExpression,
)
-from pyGHDL.dom.Concurrent import ConcurrentBlockStatement
+from pyGHDL.dom.Concurrent import ConcurrentBlockStatement, EntityInstantiation, ConfigurationInstantiation, ComponentInstantiation
from pyGHDL.dom.Subprogram import Function, Procedure
from pyGHDL.dom.Misc import Alias
from pyGHDL.dom.PSL import DefaultClock
@@ -796,40 +796,30 @@ def GetStatementsFromChainedNodes(
instantiatedUnit = nodes.Get_Instantiated_Unit(statement)
instantiatedUnitKind = GetIirKindOfNode(instantiatedUnit)
if instantiatedUnitKind == nodes.Iir_Kind.Entity_Aspect_Entity:
- entityId = nodes.Get_Entity_Name(instantiatedUnit)
- entityName = GetNameFromNode(entityId)
-
- architectureName = ""
- architectureId = nodes.Get_Architecture(instantiatedUnit)
- if architectureId != nodes.Null_Iir:
- architectureName = GetNameOfNode(architectureId)
+ entityInstance = EntityInstantiation.parse(statement, instantiatedUnit, label)
print(
- "Instance of '{component!s}({architecture})' with label '{label}' at line {line}".format(
- component=entityName,
- architecture=architectureName,
- label=label,
+ "Entity '{entity!s}({architecture})' instantiated with label '{label}' at line {line}".format(
+ entity=entityInstance.Entity,
+ architecture=entityInstance.Architecture,
+ label=entityInstance.Label,
line=pos.Line,
)
)
elif instantiatedUnitKind == nodes.Iir_Kind.Entity_Aspect_Configuration:
- configurationId = nodes.Get_Configuration_Name(instantiatedUnit)
- configurationName = GetNameFromNode(configurationId)
+ configurationInstance = ConfigurationInstantiation.parse(statement, instantiatedUnit, label)
print(
- "Instance of '{configuration}' with label '{label}' at line {line}".format(
- configuration=configurationName, label=label, line=pos.Line
+ "Configuration '{configuration}' instantiated with label '{label}' at line {line}".format(
+ configuration=configurationInstance.Configuration, label=configurationInstance.Label, line=pos.Line
)
)
- elif instantiatedUnitKind in (
- nodes.Iir_Kind.Simple_Name,
- nodes.Iir_Kind.Parenthesis_Name,
- ):
- componentName = GetNameFromNode(instantiatedUnit)
+ elif instantiatedUnitKind == nodes.Iir_Kind.Simple_Name:
+ configurationInstance = ComponentInstantiation.parse(statement, instantiatedUnit, label)
print(
"Component '{component}' instantiated with label '{label}' at line {line}".format(
- component=componentName, label=label, line=pos.Line
+ component=configurationInstance.Component, label=label, line=pos.Line
)
)
else:
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl
index eae346375..3c518cce4 100644
--- a/testsuite/pyunit/Current.vhdl
+++ b/testsuite/pyunit/Current.vhdl
@@ -85,7 +85,7 @@ architecture behav of entity_1 is
package inner_pack is
end package;
begin
- process(Clock)
+ proc: process(Clock)
begin
if rising_edge(Clock) then
if Reset = '1' then
@@ -95,6 +95,36 @@ begin
end if;
end if;
end process;
+
+ a <= b;
+
+
+ inst1: entity work.counter1(rtl)
+ generic map (
+ BITS => 8
+ )
+ port map (
+ clk => Clock
+ );
+
+ inst2: component counter2
+ port map (
+ clk => Clock
+ );
+
+ inst3: configuration counter3
+ port map (
+ clk => Clock
+ );
+
+ blk: block
+ begin
+ inst4: entity work.counter4(rtl)
+ port map (
+ clk => Clock
+ );
+ end block;
+
end architecture behav;
package package_1 is
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-31 18:29:46 +0000