diff options
| -rw-r--r-- | src/std_names.adb | 1 | ||||
| -rw-r--r-- | src/std_names.ads | 7 |
2 files changed, 5 insertions, 3 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index bdc11e695..34aae433c 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -641,6 +641,7 @@ package body Std_Names is Def ("to_unsigned", Name_To_Unsigned); Def ("to_signed", Name_To_Signed); Def ("resize", Name_Resize); + Def ("std_match", Name_Std_Match); Def ("math_real", Name_Math_Real); Def ("ceil", Name_Ceil); Def ("log2", Name_Log2); diff --git a/src/std_names.ads b/src/std_names.ads index a00d89585..e20db31a9 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -722,9 +722,10 @@ package Std_Names is Name_To_Unsigned : constant Name_Id := Name_First_Ieee + 020; Name_To_Signed : constant Name_Id := Name_First_Ieee + 021; Name_Resize : constant Name_Id := Name_First_Ieee + 022; - Name_Math_Real : constant Name_Id := Name_First_Ieee + 023; - Name_Ceil : constant Name_Id := Name_First_Ieee + 024; - Name_Log2 : constant Name_Id := Name_First_Ieee + 025; + Name_Std_Match : constant Name_Id := Name_First_Ieee + 023; + Name_Math_Real : constant Name_Id := Name_First_Ieee + 024; + Name_Ceil : constant Name_Id := Name_First_Ieee + 025; + Name_Log2 : constant Name_Id := Name_First_Ieee + 026; Name_Last_Ieee : constant Name_Id := Name_Log2; -- Verilog Directives. |