testsuite/synth: add a test for previous commit

3 files changed, 85 insertions, 0 deletions

diff --git a/testsuite/synth/null01/null01.vhdl b/testsuite/synth/null01/null01.vhdl
new file mode 100644
index 000000000..efb977339
--- /dev/null
+++ b/testsuite/synth/null01/null01.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity null01 is
+    port (sel    : std_ulogic_vector(7 downto 0);
+          d_in   : std_ulogic_vector(63 downto 0);
+          d_out  : out std_logic_vector(63 downto 0));
+end;
+
+architecture rtl of null01 is
+    subtype idx_t is integer range 0 to 0;
+
+    type reg_t is record
+      idx          : idx_t;
+      dummy : std_logic;
+    end record;
+    signal r : reg_t;
+
+    type mem_t is array(idx_t) of std_ulogic_vector(63 downto 0);
+    signal mem   : mem_t;
+begin
+    process(all)
+        variable data_out : std_ulogic_vector(63 downto 0);
+        variable j        : integer;
+    begin
+        data_out := mem(r.idx);
+        for i in 0 to 7 loop
+            j := i * 8;
+            if sel(i) = '1' then
+                data_out(j + 7 downto j) := d_in(j + 7 downto j);
+            end if;
+        end loop;
+
+	d_out <= data_out;
+    end process;
+end;
diff --git a/testsuite/synth/null01/null02.vhdl b/testsuite/synth/null01/null02.vhdl
new file mode 100644
index 000000000..315dc1257
--- /dev/null
+++ b/testsuite/synth/null01/null02.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity null02 is
+    port (sel      : std_ulogic_vector(7 downto 0);
+          d_in    : std_ulogic_vector(63 downto 0);
+          d_out        : out std_logic_vector(63 downto 0));
+end;
+
+architecture rtl of null02 is
+    subtype idx_t is integer range 0 to 0;
+
+    type reg_t is record
+      idx          : idx_t;
+      dummy : std_logic;
+    end record;
+    signal r : reg_t;
+
+    type mem_t is array(idx_t) of std_ulogic_vector(63 downto 0);
+    constant mem   : mem_t := (0 => x"fedcba9876543210");
+begin
+    process(all)
+        variable data_out : std_ulogic_vector(63 downto 0);
+        variable j        : integer;
+    begin
+        data_out := mem(r.idx);
+        for i in 0 to 7 loop
+            j := i * 8;
+            if sel(i) = '1' then
+                data_out(j + 7 downto j) := d_in(j + 7 downto j);
+            end if;
+        end loop;
+
+	d_out <= data_out;
+    end process;
+end;
diff --git a/testsuite/synth/null01/testsuite.sh b/testsuite/synth/null01/testsuite.sh
new file mode 100755
index 000000000..216074e1d
--- /dev/null
+++ b/testsuite/synth/null01/testsuite.sh
@@ -0,0 +1,13 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+for t in null01 null02; do
+    synth_analyze $t
+done
+
+clean
+
+echo "Test successful"