testsuite/synth: add tests for previous commit

3 files changed, 49 insertions, 0 deletions

diff --git a/testsuite/synth/mem02/ram8.vhdl b/testsuite/synth/mem02/ram8.vhdl
new file mode 100644
index 000000000..93160f584
--- /dev/null
+++ b/testsuite/synth/mem02/ram8.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ram8 is
+  port (val : out std_logic_vector (7 downto 0);
+        addr : std_logic_vector (3 downto 0);
+        clk : std_logic);
+end ram8;
+
+architecture behav of ram8 is
+  type mem_t is array (15 downto 0) of std_logic_vector(7 downto 0);
+  signal mem : mem_t;
+begin
+  process (clk)
+    variable ra : natural;
+  begin
+    if rising_edge (clk) then
+      ra := to_integer(unsigned (addr));
+      val <= mem(ra);
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/ram9.vhdl b/testsuite/synth/mem02/ram9.vhdl
new file mode 100644
index 000000000..71b30f6a3
--- /dev/null
+++ b/testsuite/synth/mem02/ram9.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ram8 is
+  port (val : out std_logic_vector (7 downto 0);
+        addr : std_logic_vector (3 downto 0);
+        clk : std_logic);
+end ram8;
+
+architecture behav of ram8 is
+begin
+  process (clk)
+    type mem_t is array (15 downto 0) of std_logic_vector(7 downto 0);
+    variable mem : mem_t;
+    variable ra : natural;
+  begin
+    if rising_edge (clk) then
+      ra := to_integer(unsigned (addr));
+      val <= mem(ra);
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/testsuite.sh b/testsuite/synth/mem02/testsuite.sh
index bd199178b..fd8a749c3 100755
--- a/testsuite/synth/mem02/testsuite.sh
+++ b/testsuite/synth/mem02/testsuite.sh
@@ -13,4 +13,7 @@ for t in dpram1 ram3 ram4 ram6; do
     clean
 done
 
+synth ram8.vhdl -e > syn_ram8.vhdl
+synth ram9.vhdl -e > syn_ram9.vhdl
+
 echo "Test successful"