testsuite/synth: add a test for unbounded ports.

3 files changed, 73 insertions, 0 deletions

diff --git a/testsuite/synth/uassoc01/tb_uassoc01.vhdl b/testsuite/synth/uassoc01/tb_uassoc01.vhdl
new file mode 100644
index 000000000..1e34bf4cb
--- /dev/null
+++ b/testsuite/synth/uassoc01/tb_uassoc01.vhdl
@@ -0,0 +1,23 @@
+entity tb_uassoc01 is
+end tb_uassoc01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_uassoc01 is
+  signal i1 : std_logic_vector(3 downto 0);
+  signal i2 : std_logic_vector(7 downto 0);
+  signal o  : std_logic_vector(3 downto 0);
+begin
+  dut: entity work.uassoc01
+    port map (i1, i2, o);
+
+  process
+  begin
+    i1 <= "1100";
+    i2 <= b"1010_1010";
+    wait for 1 ns;
+    assert o = "0110" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/uassoc01/testsuite.sh b/testsuite/synth/uassoc01/testsuite.sh
new file mode 100755
index 000000000..bcbdf419d
--- /dev/null
+++ b/testsuite/synth/uassoc01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in uassoc01; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"
diff --git a/testsuite/synth/uassoc01/uassoc01.vhdl b/testsuite/synth/uassoc01/uassoc01.vhdl
new file mode 100644
index 000000000..d9ec2b354
--- /dev/null
+++ b/testsuite/synth/uassoc01/uassoc01.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity uassoc01_sub is
+  port (i : std_logic_vector;
+        o : out std_logic_vector);
+end uassoc01_sub;
+
+architecture behav of uassoc01_sub is
+begin
+  o <= not i;
+end behav;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity uassoc01 is
+  port (i1 : std_logic_vector(3 downto 0);
+        i2 : std_logic_vector(7 downto 0);
+        o : out std_logic_vector(3 downto 0));
+end uassoc01;
+
+architecture rtl of uassoc01 is
+  signal o1: std_logic_vector(3 downto 0);
+  signal o2: std_logic_vector(7 downto 0);
+begin
+  dut1: entity work.uassoc01_sub
+    port map (i => i1, o => o1);
+
+  dut2: entity work.uassoc01_sub
+    port map (i => i2, o => o2);
+
+  o <= o1 xor o2 (3 downto 0);
+end rtl;