testsuite/synth: add test for 0 bit bus. For #1080

2 files changed, 31 insertions, 1 deletions

diff --git a/testsuite/synth/issue1080/repro4.vhdl b/testsuite/synth/issue1080/repro4.vhdl
new file mode 100644
index 000000000..adcb1b4e2
--- /dev/null
+++ b/testsuite/synth/issue1080/repro4.vhdl
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro4 is
+  generic (
+    num : natural := 1);
+  port (
+    clk : std_logic;
+    o : out std_logic);
+end;
+
+architecture behav of repro4 is
+  signal s : natural range 0 to num - 1 := 0;
+begin
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if s = 0 then
+        o <= '1';
+      else
+        o <= '0';
+      end if;
+      if s = num - 1 then
+        s <= 0;
+      else
+        s <= s + 1;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1080/testsuite.sh b/testsuite/synth/issue1080/testsuite.sh
index edb7da40a..06c7b7061 100755
--- a/testsuite/synth/issue1080/testsuite.sh
+++ b/testsuite/synth/issue1080/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in repro repro2 repro2_1 repro3; do
+for t in repro repro2 repro2_1 repro3 repro4; do
     synth $t.vhdl -e $t > syn_$t.vhdl
     analyze syn_$t.vhdl
     clean