testsuite/gna: add a test for #1999

4 files changed, 82 insertions, 0 deletions

diff --git a/testsuite/gna/issue1999/t1_p.vhdl b/testsuite/gna/issue1999/t1_p.vhdl
new file mode 100644
index 000000000..cc55b6883
--- /dev/null
+++ b/testsuite/gna/issue1999/t1_p.vhdl
@@ -0,0 +1,38 @@
+-----
+---  testcase for operator overload "/"
+-----
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.unsigned;
+use ieee.numeric_std.resize;
+
+package t1_p is
+  function resize(signal i : std_logic_vector; constant n : integer)
+    return std_logic_vector;
+  function "/" (signal a : std_logic_vector; signal b : std_logic_vector)
+    return std_logic_vector;
+end package t1_p;
+
+package body t1_p is
+  function resize(
+    signal i : std_logic_vector; constant n : integer) return std_logic_vector is
+  begin
+    return std_logic_vector(ieee.numeric_std.resize(unsigned(i), n));
+  end function;
+
+  -- purpose: or signals with different sizes
+  function "/" (   -- this is NOT a divider operand  !!!
+    signal a : std_logic_vector;
+    signal b : std_logic_vector)
+    return std_logic_vector is
+    variable s : integer;
+  begin  -- 
+    s := a'length;
+    if b'length > a'length then
+      s := b'length;
+    end if;
+    return resize(a, s) or resize(b, s);
+  end "/";
+end t1_p;
+
diff --git a/testsuite/gna/issue1999/t2.vhdl b/testsuite/gna/issue1999/t2.vhdl
new file mode 100644
index 000000000..09c56cb4f
--- /dev/null
+++ b/testsuite/gna/issue1999/t2.vhdl
@@ -0,0 +1,10 @@
+library ieee;
+use ieee.numeric_bit.all;
+
+entity t2 is
+end;
+
+architecture behav of t2 is
+begin
+  assert rising_edge('1');
+end behav;
diff --git a/testsuite/gna/issue1999/tc.vhdl b/testsuite/gna/issue1999/tc.vhdl
new file mode 100644
index 000000000..410a3092a
--- /dev/null
+++ b/testsuite/gna/issue1999/tc.vhdl
@@ -0,0 +1,24 @@
+--
+-- test for overloaded "/" function
+-- or signals of different size 
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.t1_p.all;
+
+entity tc is
+        port (
+     a : in std_logic_vector(1 downto 0);
+     b : in std_logic_vector(3 downto 0);
+     c : in std_logic_vector(2 downto 0);
+     o : out std_logic_vector(3 downto 0));
+end entity tc;
+
+
+architecture rtl of tc is
+begin
+        --o <= a / b;   -- this works !
+        o <=  a / b / c;   -- overloaded or function  <----  tc.vhd:19:17 
+        -- o <= ("00" & a) or b or ("0" & C);
+end architecture rtl;
diff --git a/testsuite/gna/issue1999/testsuite.sh b/testsuite/gna/issue1999/testsuite.sh
new file mode 100755
index 000000000..6615b62e9
--- /dev/null
+++ b/testsuite/gna/issue1999/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze t1_p.vhdl
+analyze_failure tc.vhdl
+
+clean
+
+echo "Test successful"