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author | Tristan Gingold <tgingold@free.fr> | 2019-10-14 21:58:30 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-14 21:58:30 +0200 |
commit | 9800901df71f3823b6bd8edd5a8548a0c8ab5098 (patch) | |
tree | cc09b25e9bbe7daa08029cc8df848c51f6be3764 /testsuite | |
parent | b029b0a43111143a0790aefa677beecb289e2b4a (diff) | |
download | ghdl-9800901df71f3823b6bd8edd5a8548a0c8ab5098.tar.gz ghdl-9800901df71f3823b6bd8edd5a8548a0c8ab5098.tar.bz2 ghdl-9800901df71f3823b6bd8edd5a8548a0c8ab5098.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/dff03/dff07.vhdl | 23 | ||||
-rw-r--r-- | testsuite/synth/dff03/tb_dff07.vhdl | 63 | ||||
-rwxr-xr-x | testsuite/synth/dff03/testsuite.sh | 2 |
3 files changed, 87 insertions, 1 deletions
diff --git a/testsuite/synth/dff03/dff07.vhdl b/testsuite/synth/dff03/dff07.vhdl new file mode 100644 index 000000000..428b527f4 --- /dev/null +++ b/testsuite/synth/dff03/dff07.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff07 is + port (q1, q2 : out std_logic; + d : std_logic; + en1 : std_logic; + en2 : std_logic; + clk : std_logic); +end dff07; + +architecture behav of dff07 is +begin + process (clk) is + begin + if rising_edge (clk) and en1 = '1' then + if en2 = '1' then + q1 <= d; + q2 <= d; + end if; + end if; + end process; +end behav; diff --git a/testsuite/synth/dff03/tb_dff07.vhdl b/testsuite/synth/dff03/tb_dff07.vhdl new file mode 100644 index 000000000..cbed9caa9 --- /dev/null +++ b/testsuite/synth/dff03/tb_dff07.vhdl @@ -0,0 +1,63 @@ +entity tb_dff07 is +end tb_dff07; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_dff07 is + signal clk : std_logic; + signal en1 : std_logic; + signal en2 : std_logic; + signal din : std_logic; + signal dout : std_logic; +begin + dut: entity work.dff07 + port map ( + q1 => dout, + d => din, + en1 => en1, + en2 => en2, + clk => clk); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + en1 <= '1'; + en2 <= '1'; + din <= '0'; + pulse; + assert dout = '0' severity failure; + + din <= '1'; + pulse; + assert dout = '1' severity failure; + + en1 <= '0'; + din <= '0'; + pulse; + assert dout = '1' severity failure; + + en1 <= '1'; + din <= '0'; + pulse; + assert dout = '0' severity failure; + + en2 <= '0'; + din <= '1'; + pulse; + assert dout = '0' severity failure; + + en2 <= '1'; + din <= '1'; + pulse; + assert dout = '1' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/dff03/testsuite.sh b/testsuite/synth/dff03/testsuite.sh index f0c94f7f9..5700e4cef 100755 --- a/testsuite/synth/dff03/testsuite.sh +++ b/testsuite/synth/dff03/testsuite.sh @@ -2,7 +2,7 @@ . ../../testenv.sh -for t in dff01 dff02 dff03 dff04 dff05 dff06; do +for t in dff01 dff02 dff03 dff04 dff05 dff06 dff07; do analyze $t.vhdl tb_$t.vhdl elab_simulate tb_$t clean |